Module 6

Power Distribution

By
S. D. Ruikar
 Syllabus

The power supply network (Local loads, Signal loads),

Local Regulation, Logic loads and on-chip power
supply distribution (Logic current profile, IR drops,
Area Bonding, On-chip by-pass capacitor), Power
supply isolation (Supply-supply isolation, Signal-
supply isolation), Bypass capacitors, Power
Distribution System
Outline
Power supply network
inductances and resistance
local loads and signal loads
Off-chip power distribution
decoupling capacitor hierarchy
Local regulations of operating voltages
On-chip power supply distribution
Power supply isolation & substrate noise mechanism on-chip
Overview
The Power-Distribution Problem Bypass Capacitors
DC supply voltage with small tolerance parasitic L and R in capacitors make
AC current, large di/dt them effective only below a certain
Inductive and resistive supply components frequency
Inductive Power Supply Noise
Local Regulation
L supplies low-frequency current, C series and parallel (shunt)
supplies high frequency clip voltage ripple
ripple due to current variation within each subtract AC current
cycle distribute at a more convenient voltage
transient at start/stop of load current
The power distribution problem
Modern digital systems operate at small DC voltages
1.5 to 3.3V
must be held to within 10% (or less)
and draw large AC currents
10A or more per chip, 100A per board, KA in a system
may go from 0 to full current in less than one clock cycle
over a supply network with parasitic elements
Inductance of bus bars, PC boards, packages,and bond wires
Resistance of on-chip wires
Power Distribution Problem
Modern digital systems operate at small Supply current is brought on a chip at
DC voltages specific locations
1.5 3.3 V with the tolerance of 10% chip edge
or less peripherally bonded chip
But they draw large AC currents chip edge and interior
average current may be 10 A per chip area bonded chip
and 100 A per board bonding method affects the distance
peak current may be 4 5 times the between a bonding pad and an on-chip
average current load circuit
current can change from 0 to the Current is distributed from the bonding
maximum value, or vice versa, in half a pads to the loads on thin resistive
clock cycle
metal wires
Supply network has parasitic elements the longer the path, the higher the
inductance L of the off-chip cables, resistance and the voltage drop (noise)
circuit boards, connectors, Problems are getting harder
package pins, and bond wires
lower voltages
resistance R of the on-chip wires
higher current density
they cause noise in the supply
thinner metal layers
voltage:
Vnoise = Ldi / dt + RI larger chips
Typical Power Supply Network

Tree-like structure with branching at each level

Parasitic off-chip inductance and on-chip resistance
Power and ground networks are usually symmetric (balanced)
same inductances and resistances
Bypass capacitors are inserted into each level to smoothen the voltage ripple caused
by large AC currents through the inductors
they act as fast auxiliary power supplies for components at each level
 Logic (Local) Loads and Signal
Loads
Logic loads connect a local point in
the power network to the
corresponding local point in the
ground network
current can be supplied from a
nearby bypass capacitor
Signal loads connect a local point Logic load
in the power network via a signal
wire to a distant point in the ground
Signal load
network
transmitted current IS must return
over a long path with an
impedance Zr
as a result, the receivers supply
voltage shifts with respect to the
transmitters supply voltage
causing the received voltage to
drop by Noise V can be largely rejected by using
V = Zr IS differential signaling or a transmitter-
by pass capacitor does not help generated reference
Logic Current Profile
Digital circuits draw AC-type current
high current spike at each clock edge
clock buffers
flip-flops activated by a clock edge
combinational logic activated by transitions at flip-flop outputs
interleaved current spikes, if the system contains several independent clock domains
Current draw is often very data dependent
in the worst case, all bits in a data path change the state during one clock cycle
in the best case, none of the bits change the state
on average, maybe 1/4 of the bits have a transition
For noise analysis and design of the power distribution network we must consider worst-
case power consumption
we cannot allow unlikely but possible events to cause system failures
For battery life we consider average power consumption
VP = supply voltage
I peak 1.1CloadVP
t tr = rise time
r

ks = switching activity
I avg ksCloadVP tck = clock
t
ck period
Off-chip power distribution
Power distribution principles
Use low impedance ground connections between ICs
The impedance between power pins on any two ICs should be as low as the
impedance between ground pins
There must be a low impedance bath between ground and power
This path must be LOW impedance on all frequencies of interest in order to
handle all fast charging/discharging on chip
Inductances are the limiting factor!
These will be compensated with global and local capacitors for supplying
momentary charge to chips
Typical load current
For a given clock domain, load is
usually periodic with the clock Load is often resistive, varying linearly
May stop or start in a single clock with supply voltage
cycle Some loads are high impedance,
With multiple clock domains, they constant independent of supply voltage
may drift into phase reinforcing one
another
 Response of the Power Supply
Network
Each section of the supply network is
an LC resonant circuit with a resonant
frequency c = (LC) -
load current IL sees primarily the
inductor L at low frequencies
(
<<c )
load current IL sees primarily the
capacitor C at high frequencies
capacitor
( supplies AC current!
at thec )resonant frequency =c , the
>>
total impedance (L and C in parallel) is
infinite, and the load current IL
activates oscillation average current
Bypass capacitor C must be large
enough to
supply AC current with an acceptable
ripple during each clock cycle
handle inductor start/stop (step)
transient
Inductive supply noise
Each section of the supply network is
an LC circuit
has a resonant frequency, LC = (LC)-1/2

inductor carries DC current (<< LC)

capacitor supplies AC current (>> L
LC)
Size capacitor to
supply cycle to cycle AC current with
acceptable ripple VP C IL
handle inductor start/stop transient
 Inductive power supply noise

Load currents at frequencies well below Wc see primarily the inductive

impedance whereas high frequency currents see primarily the capacitor
giving a voltage drops respectively
Bypass Capacitor Sizing (1)
Bypass capacitor must be able to Bypass capacitor must be able to keep
supply the instantaneous (AC) load the ripple below V also when the load
current during each clock period tck current is switched on or off causing
while keeping supply voltage variation sine-type oscillation in the capacitor
(ripple) less than some upper bound voltage:
V : L
sin(c t)
kQ kI t Vosc Iavg
C iVck i avg
V
ck
C 2

where Iavg is the average current (DC) Vosc V I avg

C L
provided by the inductor, and ki is the V
waveshape-dependent factor which
reflects the maximum fraction of the
average charge Qck that must be
supplied at a given instant. Typically ki
= 0.25 0.5
delta function: ki = 1
V
triangle wave: ki = 0.25
DC current: ki = 0
Bypass Capacitor Sizing (2)
In practice, the size of the bypass
capacitor is chosen according to the
worst case scenario, where the
capacitor has to cover simultane-ously
both the current spike during a clock
cycle and the start/stop response
(oscillation) :
2

C ki Iavg tck L Iavg

V Iavg
V

Iavg Iavg
ki tck L
V V

Typical values
C = 10 nF, ceramic, 23 MHz
C = 1 nF, ceramic, 50 MHz
C = 1 pF, ceramic, 160 MHz
C = 1 pF, on-chip, 4 GHz
C= 0.25 pF on chip, 64 GHZ
Sizing bypass capacitors
Bypass capacitor must be sized to
handle both types of inductive power
supply noise
ripple due to non-uniform current
L kI t
within a clock cycle i avg ck
start/stop transients Vmax Iavg CB CB
maximum ripple can happen at peak or
2
trough of transient
CB I avg ki Iavgtck
Approximate capacitance requirement
by summing the independent
max L Vmax
requirements
V I I
C B avg k avg

kt

L

i
c

Vmax
Parasitics of Bypass Capacitors
In practice, every capacitor have some
amount of parasitic lead inductance LC,
and effective series resistance RS.
Hence, the actual impedance of the
RS
capacitor is
1
ZC RS j LC
j
C LC
Parasitics limit the bandwidth of the
capacitor. They cause frequency
breakpoints, where the impedance ZC
becomes zero: C
1 1
fRC
f LC 2 LCC 2 RS
C
A simple rule of thumb: Use a capacitor
Device acts as a capacitor only below at frequencies below fLC /2 and fRC /2 !
fLC and fRC for example, a ceramic device with
Device acts as an inductor above fLC , fLC=23 MHz can be considered a good
capacitor upto 10 MHz
and as a resistor above fRC
Bypass capacitors
Bypass capacitors
Low inductance packages
Multiple power/gnd feeds Reduced inductance loops via circular
power/gnd
Power supply regulators
On-Chip Bypass Capacitors
On-chip bypass capacitors reduce the Any logic circuit contains a
symbiotic
peak-current demand on the chip-level bypass capacitance, because if a gate in a
power distribution network circuit is not switching, it places a part of its
MOS transistor with width W, length L, output load capacitance between the power
and oxide thickness tox can be used as a supplies
capacitor by connecting its source and For example, consider a logic circuit with
drain together. The capacitance of such 50000 gates of which at most 4000 switches
a device is simultaneously. Assuming that each of the
46000 unswitched gates connects 50 fF
between the supplies, the effective symbiotic
Cox r 0 WL 3.45 10
13
WL bypass capacitance of the circuit is 2.3 nF !
t
ox t
ox
For example, a 0.35 m technology
with tox = 7 nm, has the capacitance Cox
of 5 fF/m2 or 5 nF/mm2
1 0 1 0

NMOS capacitor
 Local Regulation
Clamps and shunt regulation
Supply overshoot can be reduced by clamping the local supply so that it can not exceed the
nominal voltage by more than a small amount

Fig: General form of clamp and shunt regulator

For a clamp For shunt

Q of the circuit
Clamps are inexpensive and draw no power except during voltage
overshoots. Clamps can be extensively used and can even be placed on
chip.
Shunt regulator dissipate considerable average power and tend to be
 Local Power Supply Regulation
The most efficient way to stabilize the Parallel (shunt) regulator
supply voltage is to use local regulators ZP I
L
IP = Imax
on each circuit board or even on each
chip
regulators enable the use of smaller bypass Imax IL
capacitors
Parallel or shunt regulators control current in
such a way that the supply network sees a
DC current Imax instead of spikes with
maximum peak value Imax
power consumption is large, and hence shunt
Series regulator
regulators are usually avoided
Series regulators convert a noisy distribution ID ZD
VP
voltage VD to a local stable supply voltage
VP
local supply is isolated from the impedance
ZD of the power distribution network VD IL
selecting VD > VP decreases the current ID
and hence the noise ID ZD
 Series regulator
The problem of differential power supply noise due to the inductance and
resistance of the off chip supply network can be largely eliminated by using a
local series regulator to control the supply voltage locally on each board or
even on chip or part of chip.
Local regulations does not address common mode supply noise due to signal
currents.

Power supply Network using Local regulations

 Linear regulator
On chip local regulation is usually performed with a linear regulator.
A typical on chip regulator converts a noisy 3.3 V off chip supply to a quiet 1.5 to 2.5 V on
chip supply.
Linear regulators can be used off chip as well.
Switching regulators which dissipates less power, especially for large step downs are usually
preferred.

Linear regulator for on chip local regulations

 Linear Series Regulator
Linear regulator is especially well-suited for
local on-chip regulation, because it does VLD
not require an inductor
ZLP Vref
Off-chip supply voltage VD is brought into M1
the chip via the local distribution
VD
impedances ZLP and ZLG
CB
package pins, bond wires, and resistive on-
CC VP
chip wires ZLG
IL
On-chip bypass capacitor CB smoothens the
incoming voltage into the local
distribution voltage VLD Power dissipation increases, when the
voltage drop VLDVref (head-room)
Voltage divider, formed by the PMOS
transistor M1 and the auxiliary filter across the transistor M1 is increased
capacitor CC, drops then the voltage VLD to not suitable for large stepdowns
the local supply voltage level VP If a large stepdown is needed, the best
solution is to use an off-chip switching
Feedback loop tries to keep the voltage VP
regulator
constant ( = Vref ) by controlling
continuously the resistance of the transistor
M1
 Switching Regulator
Switching regulator generates a pulse train
by sampling the distribution voltage VD with
some fixed frequency (for example 100 Vref
kHz)
This pulse train is then low-pass filtered by Pulse-Width LC Low-Pass
the LC filter of the regulator to give the Modulator Filter +
local
VP
+
supply voltage VP
Switching regulator can perform a very
D if VP < Vref, the duty factor is increased
V large stepdown (VD / Vref >> 10) with an
longer acceptable power consump-tion penalty
Feedback looppositive
comparespulsethe voltage VP to
=> VPvoltage
the reference rises V and adjust the duty
ref
if V
factor P > Vtime
(up ref, the duty factortime)
vs. cycle is decreased
of the pulse
shorter positive pulse
train accordingly
=> VP falls
if VP = Vref, the duty factor is not changed
 Switching Regulator
For off-chip local regulation, where inductors can be used, a
switching regulator is typically employed to permit larger
voltage step-downs and greater power efficiencies.
 Fly back switching regulator

Inverting type switching regulator

On-chip power distribution
Overview
Power is distributed on-chip from power
pads to point of use
from edges for peripheral-bonded chips
Load profile is determined by
characteristics of logic
fan-out and select
The distribution network is sized to handle
the worst-case current while keeping the
IR drops within margins
On-chip bypass capacitors can reduce
the amount of metal needed for
distribution
change peak requirement to average
requirement
Symbiotic bypass capacitors are
always present
this is why most circuits
work!
Isolate delicate circuits from noisy
circuits
The on-chip power distribution problem
Supply current is brought on chip Current is distributed from the bond
at specific locations pads to the loads on thin metal wires
on the edge for most chips which 0.04/ typical
are Load currents may be very high
peripherally bonded
average current may be as large as
distributed over the area of the chip
20A for very hot chips (50W at 2.5V)
for
peak current may be 4-5x this amount
area bonded (C4, solder ball) chips
(100A!)
Loads consume this current at different L di/dt of bond wire and IR drop
locations on the chip at different times
across on-chip wires are often a major
There is often a large parasitic source of supply noise
inductance associated with each bond-
wire or solder-ball (0.1-10nH)
Power distribution trends
The on-chip power distribution
problem is getting much harder as
technology evolves
Combination of
lower voltages
higher current density
thinner metal layers
larger chips
We are quickly approaching the point
where peripheral bonding will not be
adequate for high-performance chips
Logic current profile
Why does on-chip logic produce a
spikey current profile?
Consider the logic that generates the
current
Current is drawn to charge gate and
wire capacitance Q=CV, E=CV2
Typical behavior includes
circuit idle before clock edge
very little current
exponential clock amplification just
before clock edge
exponential ramp up in current
flip-flops are clocked
current depends on activity
factor
Fanout in a logic circuit
exponential ramp up in current
Fan-in or selection in a logic circuit
drop in current
Logic current profile
Worst-case vs. average logic current profile
Current drawn is often very data For battery life we may consider
dependent average power
e.g., a data path may switch 64-bits
from all 0s to all 1s
on average only 1/4 of the bits will
have this transition when there is
a transition at all
For noise analysis we must
consider
worst-case power
cannot allow possible, but unlikely
events to cause system failure
IR-drops
Power distribution network is designed
to keep IR drop on VDD and GND
networks within limits
e.g., for 10% supply variation, can
drop at most 5% on each supply
Networks are usually designed
specifically for the loads of a given
chip.
However, we can gain insight into the
process by considering a uniform
load
For example, suppose current densities
are
Jpeak = 0.3A/mm2
Javg = 0.05A/mm2
For a peripheral bonded chip, VDD and
GND are usually distributed by combs
with interdigitated fingers
a hierarchy of such combs is often
used
How much of a metal layer (or how
many layers) do we need to distribute
this power
 On-Chip IR Drops (1)
Voltage drops (IR drops) across the
resistive on-chip power distribution network
(VP, GND) are the major source of on-chip
power supply noise
Distribution network is designed to keep
these drops within certain limits
for example, if we allow 10 % supply voltage
variation, each supply (VP, GND) can drop at
most 5 %
To minimize resistive drops GND
supply lines must be wide/thick enough
VP
distance between a power pad and a circuit
on the chip must be minimal. In a
peripherally bonded chip, use Power ring Global power/ground
bus
several supply pads at every chip edge
power and ground rings that circle the The most efficient way to reduce IR
chip connecting the pads
drops is to use area bonding, where
separate rings for logic and I/O
supply pads are regularily distributed
regular comb-like distribution
over the whole area of the chip !
network
1mm distance to a supply pin is
always
Resistive IR drops
 On-Chip IR Drops (2)
Assume that a global power bus on a If kP is the fraction of the metal layer
peripherally bonded chip has the length LP (chip area) devoted to the power buses
(from a chip edge to the opposite edge), of one polarity (VP or GND), then
width WP, and square resistance Rsq. of the N bus segments with the area
each
LPWP/(2N) supplies power to circuits in
If half of the bus (from a chip edge to the
center) is divided into N equivalent an area of
segments, the resistance RP of each segment AP LPWP
is: 2N k P
Hence, the peak current drawn by each
LR segment is Jpk AP , where Jpk is the peak
RP
2NW
P sqP
current density

It can be shown that if N , the
VP (GND) VP (GND) voltage drop across a power bus of the
length LP / 2 (from a chip edge to the
centre ) is
pad LP / 2 LP / 2 pad
J pk Rsq L2P
VIR
8 P
k
Drop does not actually depend on the
bus width but on the fraction kP !
 On-Chip IR Drops (3)
For example, assume that we require VIR The good news is that we can size the
125 mV, and: power distribution network for average
Jpk = 0.3 A/mm2 current, if we use local on-chip bypass
Rsq = 0.04 /square capacitors to supply peak current !
LP = 15 mm
For example, if we want to distribute
power on two metal layers (kP=1) but
Then:
J pk Rsq L2P have still VIR 125 mV, we need to
VIR reduce Jpk from 0.3 to 0.1 A/mm2. This
8
kPJ R 2 is achieved by using an on-chip bypass
kP pk sq L P capacitor of the size
8VIR 2
67 pC/mm 267 pF/mm2
0.3 0.04 C 2 0.125
158
2
V
2.7 0.125
67 pC/mm2
In other words, to achieve VIR 125 mV,
almost 3 whole metal layers should be
reserved for both VP and GND, i.e., 6 metal
layers for power distribution only !!
Quite obviously, this is not acceptable
Metal Migration on a Chip
In long on-chip wires, current density
must be kept low to avoid large IR
drops
In short on-chip wires and vias, current
density must still be kept low to avoid
metal migration
High current density erodes metal and
eventually destroys the wire
wire is like a fuse
Typical value is 1 mA/m2
To avoid such migration effect the
fraction kP of metal devoted to each
power bus (VP or GND) has to satisfy
10 3
kP J avg LP
2H
where H is the thickness of the metal
layer, and the average current density Javg
is in A/mm2
Reduction of resistive IR drops
On-chip bypass capacitors
The good news is that the power Suppose we want to distribute power
distribution network doesnt really on just two metal layers (kP=1) but
need to carry all of the peak keep the drop on each supply to
current 0.125V
Much of the difference between peak Need to reduce peak current from
and average current may be 0.3A/mm2 to 0.1A/mm2
supplied by local, on-chip bypass
capacitors
Bypass capacitors are also critical
in mitigating the effects of the
supply bond-wire inductance
On-chip by-pass capacitors
On-chip by-pass capacitors
On-chip bypass capacitors current profile

0.3 Capacitor must

J (A/mm2)
supply this charge
0.1
0
0 1 2 3
t (ns)
2

Q
2
0.3A/mm 1 10 0.5
2 9 2

3
2
67pC/mm
C Q 67pC/mm 267pF/mm2
V
0.25V
On chip bypass capacitors
We need a bypass capacitor of about
0.25nF for each 1mm2 area of the chip
For comparison, an MOS capacitor
covering a 1mm2 area has a
capacitance of about 5nF/mm2
So, our bypass capacitor uses 5% of
the silicon area!
Can be made much smaller with local
regulation
On-Chip Power Distribution Schemes

Double Layer Mesh Solid Planes

Single Layer Grid
(with high speed signal (large decap, many vias)
distribution)
Power Ground
Signal
Distributed at top-most metal layers (thicker, low R metals)
Power bus structures for mixed signal
VLSI
Power supply isolation
Chips often contain To do this we need to make sure the
noisy circuits two circuits share as little of the power
pad-drivers distribution network as possible
clock generators Typically provide separate power
large RAM arrays and/or GND pins
noise-sensitive circuits quiet GND and VDD
PLLs and DLLs
receive amplifiers
etc
We would like to isolate the noise
sensitive circuits from the noise
generated by the noisy circuits
Supply-supply isolation
Signal-supply isolation
Power bus structure: tree

Suffers from strong switching circuit power coupling to queit or non-switching

function circuits
Takes minimum chip area
Must be hand optimized at layout level
Power bus structure: star

Suffers from high IR drops on-chip

Achieves maximum switching to quiet function isolation
Usually requires custom layout
Requires less chip area than Grid
Power bus structure: grid

Gives minimum IR drop. Also gives lowest AC impedance due to inherent ground to
VDD capacitance (decoupling)
One general grid design can be used for many designs
Does not require strict partitioning of switching and non-switching functions
Provide additional shielding for crosstalk reduction. Requires largest chip area
.
Power bus structure:split
Substrate contact placement on power bus
Substrate contact placement on power bus
Substrate contact placement on power bus
Substrate contact placement on power bus
Thank you