Sequential Circuits

Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1 Q = Q0

0 0

0 1

Initial Value

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

0 1

0 0

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 0

0 1

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 1 0 1 1 0 1 Q=0

0 0

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 0 0 1 1 0 1
Q=0

1 0 0 1 0 Q=1

1 1

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1 0 1
Q=0

1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

1 0

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 0 0 1 1 0 1
Q=0

1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q

1 10

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 Latches
SR Latch
S R Q0 Q Q
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 10 0 1 1 0 1
Q=0

1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q
1 1 1 0 0 Q = Q

1 0

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 Latches
SR Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q=0 Invalid

S R Q
0 0 Q=Q=1 Invalid
0 1 1 Set
1 0 0 Reset
1 1 Q0 No change
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 Latches
SR Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q=0 Invalid

S R Q
0 0 Q=Q=1 Invalid
0 1 1 Set
1 0 0 Reset
1 1 Q0 No change
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 Controlled Latches
SR Latch with Control Input

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q Invalid
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 Controlled Latches
D Latch (D = Data) Timing Diagram
C

t
C D Q
Q0 No change Output may
0 x change
1 0 0 Reset
1 1 1 Set

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 Controlled Latches
D Latch (D = Data) Timing Diagram
C

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 Flip-Flops
Controlled latches are level-triggered

Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Flip-Flops
Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
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 Flip-Flops
Edge-Triggered D Flip-Flop
D Q

Q
Positive
Edge

D Q

Q
Negative Edge

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 Flip-Flops
JK Flip-Flop

J Q
D = JQ + KQ
K Q
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 Flip-Flops
T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ + KQ
D = TQ + TQ = T Q Q

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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q(t) Toggle
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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ + KQ
K Q 1 0 1
1 1 Q(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T Q
Q 1 Q(t)
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 Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 Reset
0 1 1
K Q 1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

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 Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 K
J Q
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q 1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ + KQ
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 Flip-Flops with Direct Inputs
Asynchronous Reset

R D CLK Q(t+1)
D Q
0 x x 0
Q
R
Reset

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 Flip-Flops with Direct Inputs
Asynchronous Reset

R D CLK Q(t+1)
D Q
0 x x 0
Q 1 0 0
R 1 1 1

Reset

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 Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset

PR PR CLR D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset

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 Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset

PR PR CLR D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset

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 Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset

PR PR CLR D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 0
CLR 1 1 1 1
Reset

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 Analysis of Clocked Sequential Circuits
The State
State = Values of all Flip-Flops

Example
AB=00

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 Analysis of Clocked Sequential Circuits
State Equations

A(t+1) = DA
= A(t) x(t)+B(t) x(t)
=Ax+Bx
B(t+1) = DB
= A(t) x(t)
= A x
y(t) = [A(t)+ B(t)] x(t)
= (A + B) x 34 / 60
 Analysis of Clocked Sequential Circuits
State Table (Transition Table)
Present Next
Input Output
State State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
A(t+1) = A x + B x
1 1 1 1 0 0 B(t+1) = A x

t t+1 t
y(t) = (A + B) x
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 Analysis of Clocked Sequential Circuits
State Table (Transition Table)
Next State Output
Present
State x=0 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

t t+1 t A(t+1) = A x + B x
B(t+1) = A x
y(t) = (A + B) x
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 Analysis of Clocked Sequential Circuits
State Diagram Next State Output
Present
State x=0 x=1 x=0 x=1
AB input/output A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10

0/1
1/0 0/1 1/0

01 11
1/0 37 / 60
 Analysis of Clocked Sequential Circuits
D Flip-Flops
Example:
x D Q A
Present Next y
Input
State State
CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A x y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
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 Analysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
Present Next Flip-Flop
I/P
State State Inputs
A B x A B JA KA JB KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
JA = B KA = B x
0 1 0 1 1 1 1 1 0
JB = x KB = A x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA QA + KA QA
1 0 1 1 0 0 0 0 0 = AB + AB + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB QB + KB QB
1 1 1 1 1 1 0 0 0 = Bx + ABx + ABx
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 Analysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
Present Next Flip-Flop
I/P
State State Inputs
A B x A B JA KA JB KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0 0 1 1 0
1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
1 40 / 60
 Analysis of Clocked Sequential Circuits
T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0
1 0 1 1 0
TA = B x TB = x
0 1 1
1 0 0 0 0 y =AB
1 0 0
1 0 1 1 1 0 1 0 A(t+1) = TA QA + TA QA
1 1 0 1 1 0 0 1 = AB + Ax + ABx
1 1 1 0 0 1 1 1 B(t+1) = TB QB + TB QB
=xB 41 / 60
 Analysis of Clocked Sequential Circuits
T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1 1 0 0 1 1 1 0/1 0/0
1/0 42 / 60
 Mealy and Moore Models
Mealy Moore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

For the same state,

state For the same state,
state
the output changes with the input the output does not change with the input

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Moore State Diagram

State / Output

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0
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 Timing Diagram
0 1 0
A 00/0 01/0
x y
B 0 0 1

11/1 10/0
No effect 1 1
CLK
x
A 0 0 1 0 0 0
State
B 0 1 0 0 1 1

y
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 Timing Diagram
0/0 1/0 0/0
A 00 01
x y
B 0/0 0/0 1/0

11 10
1/1
1/1
CLK
x
A 1
State
B 0

y
46 / 60
 Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1s

0 1
S0 / 0 S1 / 0
0 State A B
S0 0 0
0 1
0 S1 0 1
S2 1 0
S3 / 1 S2 / 0 S3 1 1
1 1
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 Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1s
Present Next
Input Output
State State
A B x A B y 0 1
0 0 0 0 0 0 S0 / 0 S1 / 0
0 0 1 0 1 0 0
0 1 0 0 0 0
0 1 1 1 0 0 0 0 1
1 0 0 0 0 0
1 0 1 1 1 0
S3 / 1 S2 / 0
1 1 0 0 0 1
1 1 1 1 1
1 1 1
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 Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1s
Present Next
Input Output
State State
A B x A B y Synthesis using D Flip-Flops
0 0 0 0 0 0
0 0 1 0 1 0 A(t+1) = DA (A, B, x)
0 1 0 0 0 0
0 1 1 1 0 0 = (3, 5, 7)
1 0 0 0 0 0 B(t+1) = DB (A, B, x)
1 0 1 1 1 0
1 1 0 0 0 1 = (1, 5, 7)
1 1 1 1 1 1
y (A, B, x) = (6, 7) 49 / 60
 Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1s

Synthesis using D Flip-Flops

B
DA (A, B, x) = (3, 5, 7) 0 0 1 0
A 0 1 1 0
= Ax + Bx x B
DB (A, B, x) = (1, 5, 7) 0 1 0 0
A 0 1 1 0
= A x + B x B x

y (A, B, x) = (6, 7) 0 0 0 0
A 0 0 1 1
= AB x 50 / 60
 Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1s

Synthesis using D Flip-Flops

DA = A x + B x
DB = A x + B x
y = AB

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 Flip-Flop Excitation Tables
Present Next F.F. Present Next F.F.
State State Input State State Input
Q(t) Q(t+1) D Q(t) Q(t+1) J K 0 0 (No change)
0 1 (Reset)
0 0 0 0 0 0 x 1 0 (Set)
0 1 1 0 1 1 x 1 1 (Toggle)
0 1 (Reset)
1 0 0 1 0 x 1 1 1 (Toggle)
1 1 1 1 1 x 0 0 0 (No change)
1 0 (Set)

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
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 Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1s

Present Next Flip-Flop

Input
State State Inputs
Synthesis using JK F.F.
A B x A B JA KA JB KB
0 0 0 0 0 0 x 0 x JA (A, B, x) = (3)
0 0 1 0 1 0 x 1 x dJA (A, B, x) = (4,5,6,7)
0 1 0 0 0 0 x x 1 KA (A, B, x) = (4, 6)
0 1 1 1 0 1 x x 1 dKA (A, B, x) = (0,1,2,3)
1 0 0 0 0 x 1 0 x JB (A, B, x) = (1, 5)
1 0 1 1 1 x 0 1 x dJB (A, B, x) = (2,3,6,7)
1 1 0 0 0 x 1 x 1 KB (A, B, x) = (2, 3, 6)
1 1 1 1 1 x 0 x 0
dKB (A, B, x) = (0,1,4,5)
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 Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1s

Synthesis using JK Flip-Flops

B B
JA = B x KA = x
0 0 1 0 x x x x
JB = x KB = A + x A x x x x A 1 0 0 1
x x
B B
0 1 x x x x 1 1
A 0 1 x x A x x 0 1
x x

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 Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1s
Present Next F.F.
Input
State State Input
A B x A B TA TB Synthesis using T Flip-Flops
0 0 0 0 0 0 0
0 0 1 0 1 0 1 TA (A, B, x) = (3, 4, 6)
0 1 0 0 0 0 1 TB (A, B, x) = (1, 2, 3, 5, 6)
0 1 1 1 0 1 1
1 0 0 0 0 1 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 1 1 1 0 0
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 Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1s

Synthesis using T Flip-Flops

TA = A x + A B x
TB = A B + B x

B B
0 0 1 0 0 1 1 1
A 1 0 0 1 A 0 1 0 1
x x

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 Homework
Mano
Chapter 5
5-1
5-3
5-6
5-8
5-9

57 / 60
 Homework
5-1 The D latch is constructed with four NAND gates and an
inverter. Consider the following three other ways for
obtaining a D latch. In each case, draw the logic diagram
and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates
for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be
needed.
(c) Use four NAND gates only (without an inverter). This
can be done by connecting the output of the upper gate
that goes to the SR latch to the input of the lower gate
instead of the inverter output.

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 Homework
5-3 Show that the characteristic equation for the complement
output of a JK flip-flop is
Q(t+1) = JQ + K Q
5-6 A sequential circuit with two D flip-flops, A and B; two
inputs, x and y; and one output, z, is specified by the
following next-state and output equations:
A(t+1) = x y + x A
B(t+1) = x B + x A
z=B
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
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 Homework
5-8 Derive the state table and the state diagram of the
sequential shown circuit. Explain the function that the
circuit performs.

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 Homework
5-9 A sequential circuit has two JK flip-flops A and B and one
input x. The circuit is described by the following flip-flop
input equations:
JA = x KA = B
JB = x KB = A
(a) Derive the state equations A(t+1) and B(t+1) by
substituting the input equations for the J and K
variables.
(b) Draw the state diagram of the circuit.

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