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DIGITAL LOGIC FAMILIES

Digital Logic Families

Gates perform one or more operations.


simply electronic circuits composed of resistors, diodes
and transistors
Originally gates were composed just from resistors and
diodes, due to expense of transistors.
Due to fabrication procedures, all gates are now
constructed exclusively from transistors.

The style in which transistors are connected


characterises each logic family or library and
gives it its unique name.
Implementation of a Switch
A semiconductor diode can be considered as
an electronic switch.
Based upon the pn-junction.

What electrical properties do we know about


the pn junction ?

potential drop of 0.7v across junction when


forward biased !
Implementation of a Switch
For a potential difference of less than 0.7 V or
one negative across the device
virtually no current flows in reverse biased mode

In all discussions, will assume an ideal


characteristic for the diode.
a voltage > 0.7 V causes conduction
Implementation of Logic
Can we use diodes in the implementation of
logic gates ?
AND Gate using Diodes
A 3-input AND gate.
extra inputs can be formed by adding extra diodes.
+5 V

A
Output
Inputs B ABC

Making a positive logic level assumption


0V 0 or L
+5V 1 or H
+5 V

AND Gate R
When all inputs are at 0V
A
Output
Inputs B ABC

C
all diodes are forward biased
current will flow through the resistor R

if all diodes are identical


current will be equally divided amongst all diodes.

If all inputs are at 0V


the output voltage must be +0.7V above the input voltage of 0 V
i.e. 0.7 V
due to positive logic 0.7V L
+5 V
AND Gate
R

A
Output
Inputs B ABC

If one or more inputs are raised to +5 V


causes those diodes to become reverse-biased.
current will still flow through the remaining diode
output will remain at 0.7 V, i.e. L.
+5 V

AND Gate R

If +5v is applied to all inputs A


Output
none of the diodes will conduct Inputs B ABC
output voltage will be +5V H C

Thus circuits behaves as an AND gate only when


all inputs are +5V (logic 1) will the output be +5V (logic 1).

Note
output voltage representing logic 0 is higher than the input
logic 0 level by 0.7 V

But
voltage at a logic level 1 is 5 V for both input and output.
AND Gate

So what what is the big deal about just 0.7v ?

if AND gates implemented by diodes are cascaded


An extra +0.7 V at a logic 0 level is added to each output
of similar circuits.

a 2nd gate would have an output at a logic 0 of 1.4 V.


a 3rd gate would have an output at a logic 0 of 2.1 V.

This is unacceptable.
Diode AND gates cannot be cascaded.
OR Gate using Diodes

A
Output
Inputs B A+B+C

R
All inputs at 0 V
output at 0 V
0V
If any input is at +5 V
diode conducts
output = (input - 0.7 V)
= 4.3 V Logic 1 H
OR Gate

The fundamental Boolean operator, the Inverter ot


NOT operator cannot be produced with diodes and
resistors alone

As a diode has limited functionality in logic circuits


The transistor plays a more important role
Bipolar Transistor Gate

Consider a bipolar transistor in logic circuits


It is operated in either two states
produces the two logic levels

fully conducting state saturated/turned on

or

fully non-conducting state cut-off state


Bipolar Transistor Gate
The simple but very practical logic inverter
Vcc = 5 V
V BE(ON) =0.7V
V BE(SAT) =0.8V
RC 1 k
V CE(SAT) =0.1V Vout

Vin RB

10 k
Metrics for Comparing Logic
Families
Logic Level
Noise Margin
Fan out
Power Dissipation
Propagation Delay
Logic Levels
Positive Logic
VIL maximum allowed voltage at input for a logic low level
VIHminimum allowed voltage at input for a logic high level

VOH 5.0 V

HIGH NMH

LS
1.5 V VIH

TW
0.7 V VIL
LOW NML VOL 0.1 V

Input Output
Metrics
Between the two levels the transistor is in the
active region,
output level is not uniquely determined
where because of the loose control on the transistor
parameters.

Hence this is a forbidden region VIH VIL

The difference between VIH and VIL is the


Transition Width.
TW V IH V IL
1.5 0.7
0.8 V
Metrics
Logic Swing is defined as the difference between
the two output voltage levels
LS VOH VOL
5.0 0.1
4.9 V

Noise Margins
NM H VOH V IH NM L V IL VOL
5.0 1.5 0.7 0.1
3.5 V 0.6 V
Noise Margin
METRIC 2: Noise Margins
Gate circuits are constructed to sustain variations
in input and output voltage levels.
variations are usually result of several different factors.

1. Batteries lose their full potential, causing the supply


voltage to drop

2. High operating temperatures may cause a drift in


transistor voltage and current characteristics

3. Spurious pulses may be introduced on signal lines by


normal surges of current in neighbouring supply lines.
Noise Margins
All these undesirable voltage variations that are
superimposed on normal operating voltage levels are
called noise.

All gates designed to tolerate a certain amount of noise on


their input and output ports.
The maximum noise voltage level that is tolerated by a
gate is called a noise margin.

Noise margin derived from I/PO/P voltage characteristic


Measured under different operating conditions
Normally supplied in documentation about gate from
manufacturer.
How to determine noise margins?
Compare input and output voltage ranges of gates in same family.
VCC (5.0) VCC (5.0)
H H
VOH (2.4)
High Noise
margin
VIH (2.0)

VIL (0.8)
Low Noise
margin
VOL (0.4)
L L
GND (0) GND (0)

Output Voltage Input Voltage


range range

output voltage range of a driving gate on LHS input voltage range


of the driven gate on RHS
Any voltage between VOH and VCC is considered H.
any voltage between 0 and VOL is considered L.
How to determine noise margins?
Similarly
Any voltage between VIH and VCC is considered H
Any voltage between 0 and VIL is considered L
The voltage difference VOH - VIH called high-level
noise margin

Any noise voltage smaller than VOH - VIH will be tolerated


and will not change the output value of the driven gate.
For the same reason, the voltage difference VIL - VOL
is called the low-level noise margin.
How to determine noise margins?
In the example of transistor-transistor logic (TTL):
VOH = 2.4 V
VIH = 2.0 V
VIL = 0.8 V
VOL = 0.4 V

Thus both high and low level noise margins are 0.4 V.
Thus any noise smaller than 0.4 V will not disturb gate
operation.

Such high noise margins, which are not available in


analog circuits, make digital designs superior to analog.
METRIC 3: Fan-out
To date have understood that each gate can
drive several other gates.

The number of gates that each gate can drive,


while providing voltage levels in the
guaranteed range is called the standard
load or fan-out.

The fan-out really depends on the amount of


electric current a gate can source or sink
while driving other gates.
Fan-out
IIH

When the gate output is H

Gate behaves as a current IIH


source since IOH flows out IOH
of the driver gate and into
the set of driven gates.
IIH
The current IOH equals the
sum of all input currents
indicated by IIH, flowing into
the driven gates.
to other gates
Fan-out
When the gate output is L IIL

Gate behaves as a current


sink since IOL flows into IIL
IOL
the gate and out of the
driven gates.
IIL

The current IOL is again


equal to the sum of all to other gates

input currents IIL, flowing


out of all the driven gates.
Fan-out
Since all gates in a logic family are constructed in
such a way that each gate requires the same IIH and
the same IIL,
can compute fan-out in the following way:

I OH I OL
Fan _ out min ,
I IH I IL
min( Logic H output fanout, Logic L output fanout)
Fan-out
Example

Input and output current for the transistor-transistor


logic (TTL) family are the following:

IOH = 400 A
IOL = 16 A
IIH = 40 A
IIL = 1.6 A

Therefore the fan-out is ?


Fan-out
This means that each gate can drive 10 other
gates in the same family
without getting out of its guaranteed range of
operation.

In cases where more than 10 gates are


connected to the output of a single gate of this
family, the output voltage levels will degrade
and the gate will slow down.

Modern MOS logic families have a fan-out of


about 50,
since each gate must source or sink a current only
during the transition from H to L or L to H.
Propagation Delay
The switching times of the Bipolar junction transistor

Calculated by carrying out analysis of the charge-control


model of the BJT.
5V
5 s
0V
vi(t)

t0 t1 t2 t3 t4 t5

5V
vo(t)

0.1 V

Delay time : td= t1-t0 Saturation time : ts= t4-t3

Fall time : tf= t2-t1 Rise time : tr= t5-t4


Propagation Delay
Qualitative analysis of the switching sequences:

If the input voltage is a rectangular pulse at time t0,


it can be assumed that the input abruptly changes from 0 to 5V

As the input had previously been 0 V


Transistor had been in the Cut-off.
Output voltage is VCC = 5 V
5V

Propagation Delay 0V
5 s

vi(t)

t0 t1 t2 t3 t4 t5

5V
vo(t)

0.1 V

Delay time : td= t1-t0 Saturation time : ts= t4-t3

Fall time : tf= t2-t1 Rise time : tr= t5-t4


At time t2 the transistor is at the edge of saturation,
thus output voltage is essentially constant at VCE(sat) (=0.1 V).

At some time t3 (in this example 5 seconds) there is another step


change in the input voltage back to 0 V.
The saturation time (t4 - t3) is due to:
the removal of the overdrive charge from the neutral base region, or
the base and collector regions.
The rise time (t5- t4) is due to:
similar to fall time, but transistor is now turning off.

At time t5, the transistor is at the edge of cutoff,


Thus the output is back to VCC.
Propagation Delay
After t5, there is another delay, which is not apparent from
the output waveform transistor

The final recovery time (t6- t5)


Base voltage changes form VBE(on) to 0 V, the quiescent input
voltage.

The switching times as calculated above are of very much


interest to the digital IC designer.

However of more interest to the digital IC user are the


propagation delay times.
These times are measured between two reference levels on the
input and output voltage waveforms.
Rise Fall
time time

90%

Input
50%

10%

90%

Output
50%

10%

tPHL tPLH
Propagation Delay
For in the inverter circuit the turn-on delay time tPHL is measured
as the output is changing from a high voltage level to a low
voltage level. tf

t PHL t d
2
4 .2
0.73
2
2.8 ns
For the turn-off delay time tPLH is measured as the output is
changing from a low voltage level to a high voltage level.
tr
t PLH t s
2
15
24
2
31 ns
Propagation Delay
Thus the average propagation delay
time is defined as:
t PHL t PLH
tp
2
2.8 31

2
17 ns

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