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A
Output
Inputs B ABC
AND Gate R
When all inputs are at 0V
A
Output
Inputs B ABC
C
all diodes are forward biased
current will flow through the resistor R
A
Output
Inputs B ABC
AND Gate R
Note
output voltage representing logic 0 is higher than the input
logic 0 level by 0.7 V
But
voltage at a logic level 1 is 5 V for both input and output.
AND Gate
This is unacceptable.
Diode AND gates cannot be cascaded.
OR Gate using Diodes
A
Output
Inputs B A+B+C
R
All inputs at 0 V
output at 0 V
0V
If any input is at +5 V
diode conducts
output = (input - 0.7 V)
= 4.3 V Logic 1 H
OR Gate
or
Vin RB
10 k
Metrics for Comparing Logic
Families
Logic Level
Noise Margin
Fan out
Power Dissipation
Propagation Delay
Logic Levels
Positive Logic
VIL maximum allowed voltage at input for a logic low level
VIHminimum allowed voltage at input for a logic high level
VOH 5.0 V
HIGH NMH
LS
1.5 V VIH
TW
0.7 V VIL
LOW NML VOL 0.1 V
Input Output
Metrics
Between the two levels the transistor is in the
active region,
output level is not uniquely determined
where because of the loose control on the transistor
parameters.
Noise Margins
NM H VOH V IH NM L V IL VOL
5.0 1.5 0.7 0.1
3.5 V 0.6 V
Noise Margin
METRIC 2: Noise Margins
Gate circuits are constructed to sustain variations
in input and output voltage levels.
variations are usually result of several different factors.
VIL (0.8)
Low Noise
margin
VOL (0.4)
L L
GND (0) GND (0)
Thus both high and low level noise margins are 0.4 V.
Thus any noise smaller than 0.4 V will not disturb gate
operation.
I OH I OL
Fan _ out min ,
I IH I IL
min( Logic H output fanout, Logic L output fanout)
Fan-out
Example
IOH = 400 A
IOL = 16 A
IIH = 40 A
IIL = 1.6 A
t0 t1 t2 t3 t4 t5
5V
vo(t)
0.1 V
Propagation Delay 0V
5 s
vi(t)
t0 t1 t2 t3 t4 t5
5V
vo(t)
0.1 V
90%
Input
50%
10%
90%
Output
50%
10%
tPHL tPLH
Propagation Delay
For in the inverter circuit the turn-on delay time tPHL is measured
as the output is changing from a high voltage level to a low
voltage level. tf
t PHL t d
2
4 .2
0.73
2
2.8 ns
For the turn-off delay time tPLH is measured as the output is
changing from a low voltage level to a high voltage level.
tr
t PLH t s
2
15
24
2
31 ns
Propagation Delay
Thus the average propagation delay
time is defined as:
t PHL t PLH
tp
2
2.8 31
2
17 ns