486:

80486 architecture:
Extension of 386
Discussions w.r.t 80386 applies to 486 also
Enhancements
486 has built in math coprocessor
It makes 486 executes math instructions 3 times as fast as
386/387 combination
Another feature included in 486 is 8K code and data
cache
In 486, pipeline scheme is 5 stage pipeline (F, D1, D2, E,
S) that allows 486 to execute instructions faster than 386
 486 fetches several instructions ahead of time
Instruction pipelining
I1 I2 I3 I4
While I1 is executing, decoding of I2 will be completed and
so on
This extensive pipelining makes it possible for 486 to execute
commonly used instructions in a single CC
Statistics:
16 bit memory write operation takes 22 CC in 8088, 4 CC in
386 and 1CC in 486
Conditional Jumps have also benefited from pipelining in 486
It takes 16/4 CC in 8088, 8/3 CC in 80386, 3/1 CC in 80486
 486 data bus, address bus, byte enable, ADS#, RDY#, INTR,
RESET, NMI, M/IO#,D/C#, W/R#, LOCK#, HOLD, HLDA,
BS16# function in the same way they do in 80386
New groups
Parity group: DP0-DP3, PCHK#
This allows 486 for parity generation/detection for memory
write/read operations
Memory WriteFor each byte it generates even parity and
outputted on lines DP0-DP3
Memory ReadStored parity bits from parity memory will be
read and applied to DP0-DP3
Parity generation and detection? For error detection
In Memory read, 486 checks parities of the bytes read with the
parties applied to DP0-DP3
If there is an error, PCHK# is asserted
 Group 2: BRDY#, BLAST#
Burst Ready signal and Burst Last signal
?
If a series of reads is to be done from successive memory
locations in 1CC then we need burst mode
Burst mode:
486 sends out the first address and BLAST# high (To
terminate burst mode this will be asserted low)
When the first data word is on data bus BRDY# is asserted
486 reads and outputs the next address and so on
When the required number has been read, BLAST# is asserted
low to terminate burst mode
Group 3: BREQ( Bus Request Output signal), BOFF# (Back
Off input signal), HOLD, HLDA
 To control sharing the local bus by multiple processors
BREQ output indicates that 80486 has generated a bus
request
To make 486 release the bus, bus controller asserts
HOLD/BOFF# input
486 will finish the current bus cycle, releases the bus and
asserts HLDA
LOCK# can be used to prevent another master from
taking over the bus during a critical operation
 Cache Control Group:
KEN#: Cache Enable input is used to determine whether
current bus cycle is cacheable or not
When 486 generates a cycle that can be cached and
KEN# is active then this cycle is cached (stored in the
internal cache)
FLUSH#: Cache Flush input forces 486 to erase the
contents of its internal cache
Page Caching Control:
PWT, PCD pins (Page Write Through and Page Cache
Disable) reflect the state of PWT and PCD bits in Page
table entry