Chapter 12

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Semiconductor
Memories
December 20, 2002
Digital Integrated Circuits2nd Memories

Chapter Overview
Memory Classification
Memory Architectures
The Memory Core
Periphery
Reliability
Case Studies

Semiconductor Memory Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random EPROM Mask-Programmed

Access Access
2
E PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM

Memory Timing: Definitions
Read cycle
READ
Write cycle
Read access Read access
WRITE
Write access
Data valid
DATA
Data written

Memory Architecture: Decoders
M bits M bits
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
A K 21
SN 22
WordN 22 WordN 22
SN 21
WordN 21 WordN 21
K 5 log2N
Input-Output Input-Output
(M bits) (M bits)
Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N

Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L 2 K Bit line
AK
Row Decoder
AK1 1 Word line
AL 2 1
M.2K
Sense amplifiers / Drivers Amplify swing to

rail-to-rail amplitude
A0
Column decoder Selects appropriate
AK2 1 word
Input-Output
(M bits)

Hierarchical Memory Architecture
Block 0 Blocki BlockP 2 1
Row
address
Column
address
Block
address
Global data bus

Control Block selector Global
circuitry amplifier/driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Block Diagram of 4 Mbit SRAM
Clock Z-address X-address
generator buffer buffer
Predecoder and block selector

Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
CS, WE I/O x1/x4 Y-address X-address

buffer buffer controller buffer buffer
Digital Integrated Circuits2nd [Hirose90] Memories

Contents-Addressable Memory
Data (64 bits)
I/O Bufers
Commands
Comparand
Mask
Address Decoder
Priority Encoder
2 Validity Bits
CAM Array
Control LogicR/W Address (9 bits) 9
2 words3 64 bits
9
Memory Timing: Approaches
Address
bus Row Address Column Address
RAS Address
Bus Address
Address transition
CAS initiates memory operation
RAS-CAS timing
DRAM Timing SRAM Timing

Multiplexed Adressing Self-timed

Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
Diode ROM MOS ROM 1 MOS ROM 2

MOS OR ROM
BL[0] BL[1] BL[2] BL[3]
WL[0]
V DD
WL[1]
WL[2]
V DD
WL[3]
V bias
Pull-down loads

MOS NOR ROM
V DD
Pull-up devices
WL[0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]

MOS NOR ROM Layout
Cell (9.5 x 7)
Programmming using the

Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion

MOS NOR ROM Layout
Cell (11 x 7)
Programmming using
the Contact Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion

MOS NAND ROM
V DD
Pull-up devices
BL [0] BL [1] BL [2] BL[3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row

MOS NAND ROM Layout
Cell (8 x 7)
Programmming using
the Metal-1 Layer Only
No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion

NAND ROM Layout
Cell (5 x 6)
Programmming using
Implants Only
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion

Equivalent Transient Model for MOS NOR
ROM
Model for NOR ROM V DD
BL
rword
WL Cbit
cword
Word line parasitics

Wire capacitance and gate capacitance
Wire resistance (polysilicon)
Bit line parasitics
Resistance not dominant (metal)
Drain and Gate-Drain capacitance

Equivalent Transient Model for MOS NAND ROM
V DD
Model for NAND ROM
BL
CL
r bit
cbit
r word
WL
cword
Word line parasitics

Similar to NOR ROM
Bit line parasitics
Resistance of cascaded transistors dominates
Drain/Source and complete gate capacitance

Decreasing Word Line Delay
Driver
WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides
Metal bypass
WL K cells Polysilicon word line
(b) Using a metal bypass
(c) Use silicides

Precharged MOS NOR ROM
f pre V DD
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

Non-Volatile Memories
The Floating-gate transistor
(FAMOS)
Floating gate Gate

D
Source Drain
tox G
tox
S
n+ p n+_
Substrate
Device cross-section Schematic symbol

Floating-Gate Transistor Programming
20 V 0V 5V
10 V 5 V 20 V 25 V
0V
22.5 V
5V
S D S D S D
Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

A Programmable-Threshold Transistor
0-state 1-state
ON
DV T
OFF
V WL V GS

FLOTOX EEPROM
Floating gate Gate I
Source Drain
2030 nm -10 V V GD
10 V
n1 n1
Substrate
p
10 nm
Fowler-Nordheim
FLOTOX transistor
I-V characteristic

EEPROM Cell
BL
WL
Absolute threshold control
is hard
VDD Unprogrammed transistor
might be depletion
2 transistor cell

Flash EEPROM
Control gate
Floating gate
erasure Thin tunneling oxide
n 1 source n1 drain
programming
p-substrate
Many other options

Cross-sections of NVM cells
Flash EPROM
Digital Integrated Circuits2nd Courtesy Intel Memories
Basic Operations in a NOR Flash Memory
Erase
cell array
BL 0 BL 1
G
12 V
0V WL 0
S D
0V WL 1
open open

Write
12 V BL 0 BL 1
G
6V
12 V WL 0
S D
0V WL 1
6V 0V

Read
BL 0 BL 1
5V
G
1V
5V WL 0
S D
0V WL 1
1V 0V

NAND Flash Memory
Word line(poly)
Unit Cell Gate

ONO
Gate FG
Oxide
Source line
(Diff. Layer)
Digital Integrated Circuits2nd Courtesy Toshiba Memories

NAND Flash Memory
Select transistor Word lines
Active area
STI
Bit line contact Source line contact
Digital Integrated Circuits2nd Courtesy Toshiba Memories

Characteristics of State-of-the-art
NVM

Read-Write Memories (RAM)
STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

6-transistor CMOS SRAM Cell
WL
V DD
M2 M4
Q
M5 Q M6
M1 M3
BL BL

CMOS SRAM Analysis (Read)
WL
V DD
BL M4
BL
Q= 0
Q= 1 M6
M5
V DD M1 V DD V DD
Cbit Cbit

CMOS SRAM Analysis (Read)
1.2
1
Voltage Rise (V)
0.8
0.6
0.4
0.2
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)

CMOS SRAM Analysis (Write)
WL
V DD
M4
Q= 0 M6
M5 Q= 1
M1
V DD
BL = 1 BL = 0

CMOS SRAM Analysis (Write)

6T-SRAM Layout
VDD
M2 M4
Q Q
M1 M3
GND
M5 M6 WL
BL BL

Resistance-load SRAM Cell
WL
V DD
RL RL
Q Q
M3 M4
BL M1 M2 BL
Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem

SRAM Characteristics

3-Transistor DRAM Cell
BL 1 BL 2
WWL
RWL WWL
M3 RWL
M1 X X V DD 2 V T
M2
V DD
CS BL1
BL2 V DD 2 V T DV
No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a 1 = V WWL-VTn

3T-DRAM Layout
BL2 BL1 GND
RWL
M3
M2
WWL
M1

1-Transistor DRAM Cell
BL
WL Write 1 Read 1
WL
M1
X GND V DD 2 V T
CS
V DD
BL
V DD /2 V
sensing
CBL
Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL V PRE = V BIT V PRE ------------
C S + CBL
Voltage swing is small; typically around 250 mV.

DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.
DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold
voltage is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

Sense Amp Operation
V BL V(1)
V PRE
DV(1)
V(0)
Sense amp activated t
Word line activated

1-T DRAM Cell
Capacitor
M 1 word
line
Metal word line
SiO2
Poly
n+ n+ Field Oxide Diffused
bit line
Inversion layer
Poly
induced by Polysilicon
Polysilicon
plate bias gate plate
Cross-section Layout
Uses Polysilicon-Diffusion Capacitance

Expensive in Area

SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells
Word line
Cell plate Capacitor dielectric layer
Insulating Layer
Cell Plate Si
Transfer gate Isolation

Refilling Poly
Capacitor Insulator Storage electrode
Storage Node Poly

Si Substrate
2nd Field Oxide
Trench Cell Stacked-capacitor Cell

Static CAM Memory Cell
Bit Bit Bit Bit
Word Bit Bit
M8 M9
M4 M5
CAM CAM
M6 M7
Word
Word S S
int
CAM CAM M3 M2
Match
M1
Wired-NOR Match Line

CAM in Cache Memory
CAM SRAM
ARRAY ARRAY
Input Drivers Sense Amps / Input Drivers
Address Tag Hit R/W Data

Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry

Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

Hierarchical Decoders
Multi-stage implementation improves performance

WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

Dynamic Decoders
Precharge devices GND GND VDD
WL3
VDD
WL 3
WL 2
WL 2 VDD
WL 1
WL 1
V DD
WL 0
WL 0
VDD A0 A0 A1 A1
A0 A0 A1 A1
2-input NOR decoder 2-input NAND decoder

4-input pass-transistor based column
decoder BL BL BL BL 0 1 2 3
S0
A0
S1
S2
A1 S3
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count

4-to-1 tree based column decoder
BL 0 BL 1 BL 2 BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches

Decoder for circular shift-register
V DD V DD V DD V DD V DD V DD
WL 0 WL 1 WL 2
f f f f f f

R f f R f f R f f
V DD

Sense Amplifiers
make V as small
C V as possible
tp = ----------------
Iav
large small
Idea: Use Sense Amplifer
small
transition s.a.
input output

Differential Sense Amplifier
V DD
M3 M4
y Out
bit M1 M2 bit
SE M5
Directly applicable to
SRAMs

Differential Sensing SRAM
V DD V DD
PC
BL BL V DD V DD
EQ
M3 M4
WL i
x M1 M2 2
x x 2
x
SE M5 SE
SE
SRAM cell i
V DD
Dif.
x Sense2
x Output
Amp
SE
Output
(a) SRAM sensing scheme (b) two stage diferential amplifier

Latch-Based Sense Amplifier
(DRAM)
EQ
BL BL
VDD
SE
SE
Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.

Charge-Redistribution Amplifier
Vref
VL VS
M1
Csmall
M2 M3 Clarge
Transient Response
2.5
Concept 2.0 VS
V in
1.5
V
VL
1.0
0.5
V ref5 3V
0.0
0.0 1.00 2.00 3.00
time(nsec)

(b) Transient response
Charge-Redistribution Amplifier
EPROM V DD
SE M4 Load
Out
Cout Cascode
V casc M3 device
Ccol
Column
WLC M2 decoder
BL
M1 CBL EPROM
WL array

Single-to-Differential Conversion
WL
BL 2
x x
Dif.
1
Cell S.A. 2
V ref
Output
How to make a good Vref?

Open bitline architecture with
dummy cells
EQ
L L1 L0 V DD R0 R1 L
SE
BLL BLR

CS CS CS CS CS CS
SE
Dummy cell Dummy cell

DRAM Read Process with Dummy Cell
3 3
2 2
BL BL
1 1
BL BL
0 0
0 1 2 3 0 1 2 3
t (ns) t (ns)
reading 0 reading 1
3
EQ WL
SE
1
0
0 1 2 3
t (ns)
control signals
Voltage Regulator
VDD
Mdrive
VREF VDL
Equivalent Model
Vbias
VREF
-
Mdrive
+
VDL

Charge Pump
V DD
2V DD 2 V T
VB
M1
V DD 2 V T
CLK A B
0V
Cpump
M2
V load
Cload V load
0V

DRAM Timing

RDRAM Architecture
Bus
Clocks
k
Data k3l memory
bus array
Column
demux packet dec.
Row
demux packet dec.

Address Transition Detection
V DD
DELAY
A0 td
ATD ATD
DELAY
A1 td
DELAY
A N2 1 td

Reliability and Yield

Sensing Parameters in DRAM
1000
CD(1F)
Vsmax(mv)
QS(1C)
100
CS(1F)
10
V DD(V)
QS 5 CS V DD /2
Vsmax 5 QS/(CS 1 CD)
4K 64K 1M 16M 256M 4G 64G

Memory Capacity (bits/chip)
Digital Integrated Circuits2nd From [Itoh01] Memories

Noise Sources in 1T DRam
BL substrate Adjacent BL
CWBL
a-particles
WL
leakage
CS
electrode
Ccross

Open Bit-line Architecture Cross Coupling
EQ
WL1 WL0 WL WL D WL0 WL1

C WBL D C WBL
BL BL
C BL Sense C BL
C C C Amplifier C C C

Folded-Bitline Architecture
WL 1 WL 1 WL 0 C WL 0 WL D WL D
WBL
BL CBL x y
C C C Sense
C C C
EQ Amplifier
BL CBL x
CWBL

Transposed-Bitline Architecture
Ccross
BL 9
BL
SA
BL
BL 99
(a) Straightforward bit-line routing
Ccross
BL 9
BL
SA
BL
BL 99
(b) Transposed bit-line architecture

Alpha-particles (or Neutrons)
a-particle
WL V DD
BL
SiO2
n1 1 2
1 2
2
1 2
1 2
1 2
1
1 Particle ~ 1 Million Carriers

Yield
Yield curves at different stages of process maturity

(from [Veendrick92])

Redundancy
Row
Redundant Address
rows
Fuse
:
Bank
Redundant
columns
Memory
Array
Column Decoder Column

Address

Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong
with
1
1 =3

Redundancy and Error Correction

Sources of Power Dissipation in
Memories
V DD
CHIP I DD 5 S C iDV if 1S I DCP
nC DE V INT f m
selected miact
C PT V INT f
I DCP
n
ROW non-selected m(n2 1)ihld

DEC ARRAY
mC DE V INT f
PERIPHERY
COLUMN DEC
VSS

Data Retention in SRAM
1.30u
1.10u
0.13m m CMOS
900n
700n
Ileakage
500n Factor 7
300n 0.18m m CMOS
100n
0.00 .600 1.20 1.80
VDD
SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM
V DD
low-threshold transistor V DD V DDL
sleep
V DD,int sleep
V DD,int
SRAM SRAM SRAM

cell cell cell SRAM SRAM SRAM
cell cell cell
V SS,int
sleep
Inserting Extra Resistance Reducing the supply voltage

Data Retention in DRAM
101
100
I ACT
21
10
Current (A)
I AC
22
10
102 3
24 Cycle time : 150 ns
10 T 5 75 C,S
I DC
25
10
26
10
15M 64M 255M 1G 4G 15G 64G
Capacity (bit)
3.3 2.5 2.0 1.5 1.2 1.0 0.8

Operating voltage (V)
0.53 0.40 0.32 0.24 0.19 0.16 0.13

Extrapolated threshold voltage at 25 C (V)

Case Studies
Programmable Logic Array
SRAM
Flash Memory

PLA versus ROM
structured approach to random logic
two level logic implementation
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLAs has drastically reduced

1. slow
2. better software techniques (mutli-level logic
synthesis)
But
Pseudo-NMOS PLA
V DD
GND GND GND GND
GND
GND
GND
V DD X0 X0 X1 X1 X2 X2 f0 f1
AND-plane OR-plane

Dynamic PLA
f AND
GND V DD
f OR
f OR
f AND
V DD X0 X0 X1 X1 X2 X2 f0 f1 GND
AND-plane OR-plane

Clock Signal Generation
for self-timed dynamic PLA
f f
f AND
Dummy AND row
f AND
tpre teval
f AND Dummy AND row f OR
f OR
(a) Clock signals (b) Timing generation circuitry

PLA Layout
AndPlane OrPlane
VDD GND
x0 x0 x1 x1 x2 x2 f0 f1
Pullupdevices Pullupdevices

4 Mbit SRAM
Hierarchical Word-line Architecture
Global word line
Sub-global word line

Local Local
word line word line

Block group
select Memory cell
Block Block
select Block 0 Block 1 select Block 2...

Bit-line Circuitry
Block
Bit-line select ATD
load
BEQ
Local WL
Memory cell
B/T B/T
CD CD
CD I/O
I/O line
I/O
Sense amplifier

Sense Amplifier (and Waveforms)
Address
I /O I /O
ATD
SEQ Block
select ATD
BS BEQ
Vdd
SA BS SA I/O Lines
SEQ GND
SEQ
SEQ
SEQ SEQ Vdd
DATA SA, SA
Dei GND
DATA
BS
Data-cut

1 Gbit Flash Memory
512Mb Memory Array 512Mb Memory Array
BL0 BL1 BL16895 BL16996 BL16897
BL33791
Word Line Driver
Word Line Driver
Word Line Driver

Word Line Driver
SGD
WL31
WL0
SGS
Block0 Block0
Block1023 Block1023
BLT0
BLT1 Bit Line Control Circuit
Sense Latches Sense Latches
(10241 32)3 8 (10241 32)3 8
Data Caches
(10241 32)3 8 Data Caches
(10241 32)3 8
I/O
Digital Integrated Circuits2nd From [Nakamura02] Memories

Writing Flash Memory
Verify level
5 0.8 V Word-line level
5 4.5 V
Number of memory cells
108
106
104
102
Result of 4 times 100
program 0V 1V 2V 3V 4V
0V 1V 2V 3V 4V Vt of memory cells
Vt of memory cells
(a)
Evolution of thresholds Final Distribution

125mm2 1Gbit NAND Flash Memory
2kB Page buffer & cache

32 word lines
x 1024 blocks
Charge pump
10.7mm
16896 bit lines
11.7mm

125mm2 1Gbit NAND Flash Memory

Technology
Technology 0.13m
0.13m p-sub
p-sub CMOS
CMOStriple-well
triple-well
1poly,
1poly,1polycide,
1polycide, 1W,
1W, 2Al
2Al

Cell
Cellsize
size 0.077m2
0.077m2

Chip
Chipsize
size 125.2mm2
125.2mm2

Organization
Organization 2112
2112xx8b8bxx64
64page
pagexx1k1kblock
block

Power
Powersupply
supply 2.7V-3.6V
2.7V-3.6V

Cycle
Cycletime
time 50ns
50ns

Read time
Readtime 25s
25s

Program
Programtime
time 200s
200s //page
page

Erase
Erasetime
time 2ms
2ms// block
block

Semiconductor Memory Trends
(up to the 90s)
Memory Size as a function of time: x 4 every three years

(updated)

Trends in Memory Cell Area

Technology feature size for different SRAM generations

Chapter 12

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Chapter 12

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Digital Integrated

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Random Non-Random EPROM Mask-Programmed

SRAM FIFO FLASH

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Sense amplifiers / Drivers Amplify swing to

Digital Integrated Circuits2nd Memories

Global data bus

Predecoder and block selector

CS, WE I/O x1/x4 Y-address X-address

Digital Integrated Circuits2nd [Hirose90] Memories

DRAM Timing SRAM Timing

Digital Integrated Circuits2nd Memories

Diode ROM MOS ROM 1 MOS ROM 2

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

BL [0] BL [1] BL [2] BL [3]

Digital Integrated Circuits2nd Memories

Programmming using the

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

BL [0] BL [1] BL [2] BL[3]

All word lines high by default with exception of selected row

Digital Integrated Circuits2nd Memories

No contact to VDD or GND necessary;

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Word line parasitics

Digital Integrated Circuits2nd Memories

Word line parasitics

Digital Integrated Circuits2nd Memories

Metal word line

(a) Driving the word line from both sides

WL K cells Polysilicon word line

(b) Using a metal bypass

(c) Use silicides

Digital Integrated Circuits2nd Memories

BL [0] BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,

Digital Integrated Circuits2nd Memories

Floating gate Gate

Device cross-section Schematic symbol

Digital Integrated Circuits2nd Memories

Avalanche injection Removing programming Programming results in

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

erasure Thin tunneling oxide

Many other options

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories

Unit Cell Gate

Digital Integrated Circuits2nd Courtesy Toshiba Memories

Bit line contact Source line contact

Digital Integrated Circuits2nd Courtesy Toshiba Memories

Digital Integrated Circuits2nd Memories

Digital Integrated Circuits2nd Memories