CMOS INVERTER

FABRICATION PROCESS

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 Sticks Diagram
V DD 3

In Out
Dimensionless layout entities
Only topology is important
Final layout generated by
1 compaction program

GND

Stick diagram of inverter

 CMOS Fabrication Process
[p-well method]

Si-substrate

Fig. (1) Pure Si single crystal

----------------------------------
-----------------------------
-----------------------------
-----------------------------
-----------------------------
Fig. (2) n-type impurity is lightly
doped
 CMOS Fabrication Process
[Step- formation of p-well]

Thick SiO2
(1 m)

----------------------------------
-----------------------------
-----------------------------
-----------------------------
-----------------------------

Fig. (3) SiO2 Deposited over si surface

 CMOS Fabrication Process
[Step- formation of p-well]

-ve Photoresist

-----------------------------------
------------------------------
------------------------------
------------------------------ Thick SiO2
------------------------------ (1 m)

Fig. (4) Photoresist is Deposited over siO2 surface

 CMOS Fabrication Process
[Step- formation of p-well]
Mask-1 UV Light

Photoresist

Mask-1 is used
for forming p-
well

-----------------------------------
------------------------------
------------------------------
------------- Thick SiO2
------------------------------ (1 m)

Fig. (5) Photoresist is Deposited over siO2 surface

 CMOS Fabrication Process
[Step- formation of p-well]

Photoresist

-----------------------------------
------------------------------
------------------------------
------------- Thick SiO2
------------------------------ (1 m)

Fig. (6) Photoresist (soft) which is not exposed is etched away.

 CMOS Fabrication Process
[Step- formation of p-well]

Photoresist

-----------------------------------
------------------------------
------------------------------
------------- Thick SiO2
------------------------------ (1 m)

Fig. (6) SiO2 which is not exposed is etched away.

 CMOS Fabrication Process
[Step- formation of p-well]

-----------------------------------
------------------------------
------------------------------
------------- Thick SiO2
------------------------------ (1 m)

Fig. (6) Photoresist (hard) is etched away.

 CMOS Fabrication Process
[Step- formation of p-well]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (7) p-type impurity is added to Si wafer through the window by diffusion process
.
 CMOS Fabrication Process
[Step- formation of Diffusion area for p-MOS]

Mask-2 Photoresist

Mask-2 is used
for forming
diffusion area for
p-MOS
-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (8) Photo resist is grown and exposed in UV Light.

 CMOS Fabrication Process
[Step- formation of Diffusion area for p-MOS]

Photoresist

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (9) Photoresist (soft) which is un-exposed etched away.

 CMOS Fabrication Process
[Step- formation of Diffusion area for p-MOS]

Photoresist

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (9) SiO2 is etched away.

 CMOS Fabrication Process
[Step- formation of Diffusion area for p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (10) Polymerised Photoresist (hard) is stripped away.

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (11) Deposit Thinox

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (12) Deposit Polysilicon

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (13) Deposit Photoresist

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

Mask-3
Mask-3 is
used for the
formation of
Two GATEs

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (14) UV Light Exposure to form GATEs of P-MOS and n-MOS

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

Mask-3
Mask-3 is
used for the
formation of
Two GATEs

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (14) Un-exposed photoresist is etched away

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

Mask-3
Mask-3 is
used for the
formation of
Two GATEs

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (14) Metal is etched away

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

Mask-3

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (15) SiO2 is etched away

 CMOS Fabrication Process
[[Step- Gate formation for n-MOS and p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (16) Polymerised Photoresist (hard) is stripped away.

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (17) Grow SiO2 Layer

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]
Mask-4 is
used for the
formation of
S and D of p-
Mask-4
MOS

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (18) Grow Photoresist Layer

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]
Mask-4 is
used for the
formation of
S and D of p-
Mask-4
MOS

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (18) Un-exposed Photoresist is etched away

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]
Mask-4 is
used for the
formation of
S and D of p-
Mask-4
MOS

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (19) SiO2 is etched away

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]
Mask-4 is
used for the
formation of
S and D of p-
Mask-4
MOS

-----------------------------------
- - - - - - - - - - - - - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (20) photoresist (hard) is Strip away

 CMOS Fabrication Process
[[Step- Source & Drain formation for p-MOS]
Mask-4 is
used for the
formation of
S and D of p-
Mask-4
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (21) Diffusion of p-type impurity

 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]
Mask-5 is
used for the
formation of
S and D of n-
Mask-5
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (22) Grow photoresist

 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]
Mask-5 is
used for the
formation of
S and D of n-
Mask-5
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (23) Un-exposed Photoresist is etched away

 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]
Mask-5 is
used for the
formation of
S and D of n-
Mask-5
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (23) SiO2 is etched away

 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]
Mask-5 is
used for the
formation of
S and D of n-
Mask-5
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- ----- -- -- -- ----- -- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1 m)

Fig. (24) Hard photoresist stripped away

 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]
Mask-5 is
used for the
formation of
S and D of n-
Mask-5
MOS

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
------------- Thick SiO2
------------------------------ (1 m)

Fig. (25) Diffusion of n-type impurity to form Source and Drain of n-MOS
 CMOS Fabrication Process
[[Step- Source & Drain formation for n-MOS]

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Diffusion of n-type impurity to form Source and Drain of n-MOS
 CMOS Fabrication Process
[[Step- Formation of Contact-Cut]

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Grow Photoresist

 CMOS Fabrication Process
[[Step- Formation of Contact-Cut]
Mask-6 is
used for the
formation of
Contact
Mask-6
Cuts in S, D
and G of n-
MOS and p-
MOS
- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Expose in UV Light

 CMOS Fabrication Process
[[Step- Formation of Contact-Cut]
Mask-6 is
used for the
formation of
Contact
Mask-6
Cuts in S, D
and G of n-
MOS and p-
MOS
- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Un-Exposed Photoresist is etched away

 CMOS Fabrication Process
[[Step- Formation of Contact-Cut]
Mask-6 is
used for the
formation of
Contact
Mask-6
Cuts in S, D
and G of n-
MOS and p-
MOS
- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) SiO2 is etched away

 CMOS Fabrication Process
[[Step- Formation of Contact-Cut]
Mask-6 is
used for the
formation of
Contact
Mask-6
Cuts in S, D
and G of n-
MOS and p-
MOS
- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Photoresist (hard) is etched away

 CMOS Fabrication Process
[[Step- Metakkization]

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Grow Metal

 CMOS Fabrication Process
[[Step- Metakkization]
Mask-7 is
used for the
deposition of
Mask-7
metal in
contact - cuts

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Grow Photoresist

 CMOS Fabrication Process
[[Step- Metakkization]
Mask-7 is
used for the
deposition of
Mask-7
metal in
contact - cuts

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Photoresist (soft) is etched away

 CMOS Fabrication Process
[[Step- Metakkization]
Mask-7 is
used for the
deposition of
metal in
contact - cuts

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Metal is etched away

 CMOS Fabrication Process
[[Step- Metakkization]
Mask-7 is
used for the
deposition of
metal in
contact - cuts

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

Fig. (25) Photoresist (hard) is etched away

 Vin

VDD
(SOURCE) Vout
GND

(SOURCE)

- - - -p- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -p- - - - -- -- -n---- -- -- -- -----n-- - - - - -
------------
- - - - - - - - - - - - - - - -- -- -- p-well
- - - - -- ---- - - - - -
-------------
------------------------------

CMOS INVERTER
 Semi Custom ASIC Technology

Semi Custom ASICs implement their functionality by using

pre-designed building blocks, called cells.
Cell of One bit Full Adder Layout of One bit Full Adder
B
A U2 U3 U4

U1

COUT
U10 U11
U5

U9 U6
U8 U7
Sum CIN

Three Bit Adder

 Various Cells

VDD VDD

NOT out
In

GND
GND

VDD
VDD

In 1 NAND2 out

In 2

GND
GND
 VHDL Role in System Design
[It is the way by which we convert the idea of our desired functionality into an implementation]

Design Idea

VHDL Model

Simulation

Simulated Waveforms

Synthesis

Circuit Generated

Circuit Implemented
 Simulation Tool

VHDL Model

Compile It
(e.g Modelsim)

Syntax
Error
Exists

Generated Waveforms
 Synthesis Tool
Inputs to Synthesis Tool are:
- HDL Description
- Device Selection (Target Technology)
- Information about design priority ( area vs speed )

Output of Synthesis Tool:

- Gate level Netlist [EDIF file]

VHDL Model
Design Priority
Information about
(area vs speed)
Device
Synthesis Tool
(e.g Leonardospectrum)

Netlist Generated for

Target Technology
 Place & Route Tool
Place tool takes the gate level netlist generated by Synthesis tool and figure out
which logic blocks in the chip should contain which logic and where these logic
blocks are placed inside the chip (this is called floor planning).
Route Tool makes interconnections between various logic blocks.

EDIF File

Place & Route Tool

Bit Map File [ for FPGA ]

GDS II File [ for cell based design ]