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ARM(Advanced RISC

Machines)

ARM versions.
ARM programming model.
ARM memory organization.
ARM data operations.
ARM flow of control.
ARM versions

ARM architecture has been extended over


several versions.
ARM 7 is specified.
Features used by ARM Processor

A load-store architecture
Fixed-length 32-bit instructions
3-address instruction formats
Load Store Architecture

The instruction set will only process values


which are in registers and will always place
results of such processing into a register.
The only operations which apply to memory
state are ones which copy memory values into
registers(load instructions) or copy register
values into memory(store instructions)
ARM will not support memory to memory
operations. Therefore ARM instructions fall into
one of the following three categories.
Date processing instructions Example add values
of two registers
Data Transfer Instructions load store instructions
Control flow instructions - Branch Instructions and
Branch link instructions.
Addressing Modes of ARM

Register Addressing
Immediate Addressing
Indirect Base and Indexed Addressing
ARM Processor Features and Variants of ARM Processor
Features of Pipeline Processing shown by Three Stage Pipeline
in ARM 7 Family Processors
Overview of Memory Organisation in ARM Family
Variants of ARM

Thumb(T Variants)
Long multiply instructions(M Variants)
Enhanced DSP instructions(E Variants)
Jazelle Version ARM architecture executes
Java codes fast due to Java accelerator
core as internal co-processor.
Overview of the CPU architecture and
programming model of Registers, Address and
Data Buses.
Block Diagram Explained
ARM programming model

r0 r8
r1 r9 0
31
r2 r10
r3 r11 CPSR
r4 r12
r5 r13
r6 r14 NZCV
r7 r15 (PC)
CPSR Format-used in user level programs to store the
condition code bits.
ARM data types

Word is 32 bits long.


Word can be divided into four 8-bit bytes.
ARM addresses can be 32 bits long.
Address refers to byte.
Address 4 starts at byte 4.
Can be configured at power-up as either
little- or bit-endian mode.
ARM status bits

Every arithmetic, logical, or shifting


operation sets CPSR(Current Program
Status Register) bits:
N (negative), Z (zero), C (carry), V
(overflow).
ARM data instructions

Basic format:
ADDr0,r1,r2
Computes r1+r2, stores in r0.
Immediate operand:
ADDr0,r1,#2
Computes r1+2, stores in r0.
ARM data instructions

ADD, ADC : add (w. AND, ORR, EOR


carry) BIC : bit clear
SUB, SBC : subtract LSL, LSR : logical shift
(w. carry) left/right
RSB, RSC : reverse ASL, ASR : arithmetic
subtract (w. carry) shift left/right
MUL, MLA : multiply ROR : rotate right
(and accumulate) RRX : rotate right
extended with C
ARM comparison
instructions

CMP : compare
CMN : negated compare
TST : bit-wise test
TEQ : bit-wise negated test
These instructions set only the NZCV bits
of CPSR.
ARM move instructions

MOV, MVN : move (negated)

MOVr0,r1;setsr0tor1
ARM load/store
instructions

LDR, LDRH, LDRB : load (half-word, byte)


STR, STRH, STRB : store (half-word, byte)
Addressing modes:
register indirect : LDRr0,[r1]
with second register : LDRr0,[r1,r2]
with constant : LDRr0,[r1,#4]
Additional addressing
modes
Base-plus-offset addressing:
LDR r0,[r1,#16]
Loads from location r1+16
Auto-indexing increments base register:
LDR r0,[r1,#16]! r1 changes before/present
Post-indexing fetches, then does offset:
LDR r0,[r1],#16 r1 changes after instrucitons
executes
Loads r0 from r1, then adds 16 to r1.
ARM flow of control

All operations can be performed


conditionally, testing CPSR:
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE,
LT, GT, LE
Branch operation:
B#100
Can be performed conditionally.
Condition Codes in ARM
Summary

Load/store architecture
Most instructions are RISC, operate in
single cycle.
Some multi-register operations take longer.
All instructions can be executed
conditionally.
PIC(Programmable Interface Controller)
Characteristics
Power-on reset
Brown out reset
Simplified instruction set
High speed execution
Watchdog timer,
Parallel slave port(PSP)
SPI,USART, analog input ports
In-circuit debugger
Free integrated development environment(IDE), assembler
and simulator.
C Version EPROM and F version Flash Memory
16F877
Block Diagram Explained
Memory Harvard Architecture
CPU of PIC processes the instructions using Harvard Architecture for
memory.
Program Counter and Internal Program Memory Bus
Program memory(flash) is 8k X 14.
Instruction length is 14-bit.
Flash saves 14 bits at each address. 8192 addresses are present in flash
in PIC 16F877.
Program counter starts from a value, which is preprogramed at the reset
vector address.
Internal Data Bus It interconnects the registers, RAM, internal
peripherals and ports. It has 8 bit width.
Instruction Cycle Time
-200ns,5MIPS
Block Diagram Explained
Register File/RAM
It is 368 Bytes in PIC 16F877. 9-bits are required to access
the RAM. Register file/RAM divides four banks. Each bank has
128 addresses and it can be accessed by the RP1:RP0 bits.
RAM/File Select Register(FSR)
It provides the 8-bit address of RAM/register in the register
file. It is used for indirect addressing in the instruction
Status Register(STATUS)
It has 8-bits. Bit 0,1,2 are C, Borrow and Z.
Bit 4 of STATUS is TO(Time-out) bit. TO=0 means the
watchdog timer time out has occurred, =1 means still not
occurred.
Block Diagram Explained
MUX and ADDRMUX
MUX takes 8-bit input from either 8 bit instruction register
during the instruction with immediate addressing.
ADDRMUX takes 8 bit input indirect address bits or 7 bits
direct address from IR(instruction register) during instruction
immediate addressing or branch or call instruction.
Block Diagram Explained
Memory and Peripherals in Architecture of PIC16F877.
Program memory size is 14 kB(8kX14 bit instructions). Program memory
type is flash.
It has RAM of 368 bytes and data EEPROM of 256 bytes.
The synchronous serial port can be configured as 3-wire Serial Peripheral
Interface (SPI) option 1. The option 2 is 2-wire Inter Integrated Circuit bus
and a Universal Asynchronous Receiver Transmitter(USART).
There are two 8bit timers, TMR0 and TMR2 2 X 8 bit.
There is one 16 bit timer, TMR1 1 X 16 bit.
There is CCP1,2. It has two capture/compare/PWM peripherals for input
capture, out-compare and pulse width modulation functions.
There is 8-input channel 10 bit ADC.
MCU operates at 2.0 V to 5.5 V and has 40 pins.
The clock oscillator and reset circuits are the internal circuits.
A XTAL is attached at two pins OSC1 and OSC2. There is 20 MHz Oscillator.
It connects the OSC1 and OSC2 pins.
Block Diagram Explained
Reset circuit, which connects to MCLR pin. MCLR/Vpp = 0 for the reset.
MCLR pin is also used as Vpp (Programming voltage). The Vpp is also
applied at this pin when programming the MCU.
One external interrupt is provided. It occurs through PORTB RB0 pin.
Harvard architecture: There is the internal flash starting from program code
address 0X0000(Program memory) accessed by 13 bits. There is the internal
RAM/register file for the SFRs/GPRs(general purpose registers/RAM) starting from
0x0000 and 0x000(Data memory). It is accessed by 7-bit direct address or 8-bit
indirect address.
Ports: There are five Ports 6 bit PORTA, 8-bit PORTB, 8-bit PORTC, 8 bit
PORTD, and 3 bit PORTE. Each port has a data-direct register TRIS. TRIS(Transmit
Receive Input Select) bit controls the direction of a port pin, whether it will be for
input or for output. These are called TRISA, TRISB, TRISC and TRISE for A,B,C,D and
E ports, respectively.
Parallel Slave Port: PSP is handshake mode port in which Port D pins are
used for PSP input/output and Port E pins are used for control signals RD,WR and CS.
PORTD can either function as general purpose port or PSP. PSP control and status
bits are at TRISE b4,b5,b6 and b7 bits and the control signals are through PORTE
when PORTD is programmed for the PSP.
Block Diagram Explained
Register file/internal RAM: Between 0x000 and 0x1FF, there is
register file/internal RAM. A register file is of 256 bytes in 4 banks(two
bank pairs). Each bank is 0f 128 byte and registers /RAM has the data at 7
bit addresses 0x00 to 0x7F in a bank. Bank base address starts from
address 0x08xbank number(0or1or2or3).
14 kB flash has the addresses of vectors, program, routines, ISRs,
and its constant data starting from 0x0000 and extending upto
0x1FFF(8192 addresses, accessible by 13 bits).
A program word is of 14-bit length. Reset vector and interrupt
vectors are between 0x0000 and 0x0004. Program memory divides into
four pages.
There is interrupt control circuit. INTCON is used for defining
control bits for timer 0 overflow, port B input change and external pin INT
interrupts. It also defines the global interrupt enable and peripherals
interrupt (service) enable.
Block Diagram Explained
There is watchdog timer unit that can be set to reset the processor
after watched-time for finishing a task is over. There are following circuits
power up timer, oscillator start up timer, power on reset ,brown out reset,
in-circuit debugger and low V programming. [ Brown-out circuit means a
circuit, which detects the voltage Vdd falling below a threshold then it
resets the MCU] Programming means writing the program codes to internal
flash memory/EPROM.
PIC 16F877 Instruction Set