Lecture #41: Active devices

• This week we will be reviewing the

material learned during the course
• Today: review
– Active circuits
– Digital logic
– CMOS transistors

12/8/2004 EE 42 fall 2004 lecture 41 1

 Example of the Load-Line Method
Lets hook our 2K resistor + 2V source circuit up to an LED (light-emitting
diode), which is a very nonlinear element with the IV graph shown below.
Again we draw the I-V graph of the 2V/2K circuit on the same axes as
the graph of the LED. Note that we have to get the sign of the voltage
and current correct!!

At the point where the two graphs intersect, the voltages and the currents
are equal, in other words we have the solution.
I (ma)
I
Solution: I = 0.7mA,
+ LED
+ 4 V = 1.4V
2V LED
- V

2K - 2

V (Volt)
5
12/8/2004 EE 42 fall 2004 lecture 41 2
 Simplification for time behavior of RC Circuits
Before any input change occurs we have a dc circuit
problem (that is we can use dc circuit analysis to relate the
output to the input).
Long after the input change
occurs things “settle down” ….

voltage
Nothing is changing …. So
again we have a dc circuit input
problem.
We call the time period during time
which the output changes the
transient

voltage
We can predict a lot about the output
transient behavior from the pre- and
post-transient dc solutions
time
12/8/2004 EE 42 fall 2004 lecture 41 3
 RC RESPONSE
Example – Capacitor uncharged: Apply voltage step of 5 V
5
Input node R Output node
Vin

Vout
+
Vout Vin C
-
0
ground
0
time
• Clearly Vout starts out at 0V ( at t = 0+) and approaches 5V.
• We know this because of the pre-transient dc solution (V=0) and
post-transient dc solution (V=5V).

So we know a lot about Vout during the transient - namely its initial value,
its final value , and we know the general shape .

12/8/2004 EE 42 fall 2004 lecture 41 4

 LOGIC GATE DELAY τ D
Time delay τ D occurs between input and output: “computation” is
not instantaneous
Value of input at t = 0+ determines value of output at later time t = τ D
F
A
B Capacitance to Ground
Logic State

Input (A and B tied together)

1

0 t
0
1 Output (Ideal delayed step-function)
F
0 t
τ D
0
Actual exponential voltage versus time.
12/8/2004 EE 42 fall 2004 lecture 41 5
 SIGNAL DELAY: TIMING DIAGRAMS
Show transitions of variables vs time
Oscilloscope Probe
A B C D Logic state
1
A
0 t
Note B changes one gate delay 0
after A switches B
τ t
Note that C changes two gate delays C
after A switches.
t
Note that D changes three gate delays
τ 2τ
after A switches. D
2 t
τ τ 3τ

12/8/2004 EE 42 fall 2004 lecture 41 6

 EXAMPLE OF THE USE OF DEPENDENT SOURCE
IN THE MODEL FOR AN AMPLIFIER

AMPLIFIER SYMBOL AMPLIFIER MODEL

Differential Amplifier V0 = A( V+ − V− ) Circuit Model in linear region
V+ + V0
A + + +
V− − Ri V1 AV1 V0
− − −

V0 depends only on input (V+ − V-)

See the utility of this: this Model when used correctly

mimics the behavior of an amplifier but omits the
complication of the many many transistors and other
components.
12/8/2004 EE 42 fall 2004 lecture 41 7
 NODAL ANALYSIS WITH DEPENDENT SOURCES
Example circuit: Voltage controlled voltage source in a branch
R1 Va R3 Vb R5 Vc

R2
+ VAA ISS
− + R4 R6
− AvVc

Write down node equations for nodes a, b, and c.

(Note that the voltage at the bottom of R2 is “known” so current
flowing down from node a is (Va − AvVc)/R2.)
Va − VAA Va − A v Vc Va − Vb
+ + =0 CONCLUSION:
R1 R2 R3
Vb − Va Vb Vb − Vc Vc − Vb Vc Standard nodal
+ + =0 + = ISS
R3 R4 R5 R5 R6 analysis works
12/8/2004 EE 42 fall 2004 lecture 41 8
 NODAL ANALYSIS WITH DEPENDENT SOURCES
Finding Thévenin Equivalent Circuits with Dependent Sources Present

Method 1: Use Voc and Isc as usual to find VT and RT

(and IN as well)
Method 2: To find RT by the “ohmmeter method” turn
off only the independent sources; let the dependent
sources just do their thing.

12/8/2004 EE 42 fall 2004 lecture 41 9

 NODAL ANALYSIS WITH DEPENDENT SOURCES
Example : Find Thévenin equivalent of stuff in red box.

Va R3 Vc

R2
ISS
+ R6
− A v Vcs

With method 2 we first find open circuit voltage (VT) and then we
“measure” input resistance with source ISS turned off.
I R (R + AR 3 ) R = R 2 (R 6 + R 3 )
You verify the solution: VTH = SS 6 2 TH
R 2 + R 3 + R 6 (1 - A) R 2 + R 3 + R 6 (1 - A)
12/8/2004 EE 42 fall 2004 lecture 41 10
 EXAMPLE: AMPLIFIER ANALYSIS
USING THE AMPLIFIER MODEL WITH Ri = infinity:
Assume the voltage between the inputs is zero, and then figure out if
that is consistent, or if the amplifier will hit a rail.
RF RF

VIN RS V- VIN RS V-
− -
V+ A V0 V1 + V0
+
V+ + AV1
−

Method: We substitute the amplifier model for the amplifier, and

perform standard nodal analysis
- AR F
solution: RIN = R F + (1 + A)R S VO/VIN =
1+ A R F + (1 + A)R S
12/8/2004 EE 42 fall 2004 lecture 41 11
 OP-AMPS AND COMPARATORS
A very high-gain differential amplifier can function either in extremely
linear fashion as an operational amplifier (by using negative feedback)
or as a very nonlinear device – a comparator. Let’s see how!
Differential Amplifier V0 = A( V+ − V− ) Circuit Model in linear region
V+ + V0
A + + +
V− − Ri V1 AV1 V0
− − −

“Differential” ⇒ V0 depends only on difference (V+ − V-)

“Very high gain” ⇒ A → ∞ But if A ~ ∞ , is the

output infinite?
The output cannot be larger than the supply voltages. It will limit or
“clip” if we attempt to go too far. We call the limits of the output the
“rails”.
12/8/2004 EE 42 fall 2004 lecture 41 12
 WHAT ARE I-V CHARACTERISTICS OF AN ACTUAL
HIGH-GAIN DIFFERENTIAL AMPLIFIER ?
• Circuit model gives the essential linear part
• But V0 cannot rise above some physical voltage related to
VIN + + V0
− − the positive power supply VCC (“ upper rail”) V0 < V+RAIL

• And V0 cannot go below most negative power supply, VEE

i.e., limited by lower “rail” V0 > V-RAIL
Example: Amplifier with gain of 105, with max V0 of 3V and min V0 of −3V.
(a) (b)
V-V near V0 (V) upper “rail”
V-V over wider V0 (V)
origin range 3
0.2 2
0.1 1

−1 VIN (µ V) VIN (µ V)
−3 −2 1 2 3 −30 −20 −10 10 20 30
−1
lower “rail”
−.2 −2
12/8/2004 EE 42 fall 2004 lecture 41 −3 13
 THE RAILS
The output voltage of an amplifier is of course limited by whatever
voltages are supplied (the “power supplies”). Sometimes we show
them explicitly on the amplifier diagram, but often they are left off.
Differential Amplifier VDD =2V

V0= A( V+ −V −) V+ V0= A( V+ −V −)
V+ + +
A A
V− − V− −

VSS =0

If the supplies are 2V and 0V, the output cannot swing beyond
these values. (You should try this experiment in the lab.) For
simplicity we will use the supply voltages as the rails.
So in this case we have upper rail = 2V, lower rail = 0V.

12/8/2004 EE 42 fall 2004 lecture 41 14

 I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN
DIFFERENTIAL AMPLIFIER (cont.)
Example: Amplifier with gain of 105, with upper rail of 3V and lower rail
of −3V. We plot the V0 vs VIN characteristics on two different scales

(c)
Same V0 vs VIN over even
wider range
(b) upper V0 (V)
V-V over V0 (V) “rail”
wide range 3 3
2 2
1 1

−30 −20 −10 VIN (µ V) VIN (V)

lower 10 20 30 −3 −2 −1 1 2 3
−1 −1
“rail” −2 −2
−3
−3

12/8/2004 EE 42 fall 2004 lecture 41 15

 Logic Gates
These are circuits that accomplish a given logic function such as “OR”. We will
shortly see how such circuits are constructed. Each of the basic logic gates has a
unique symbol, and there are several additional logic gates that are regarded as
important enough to have their own symbol. The set is: AND, OR, NOT, NAND,
NOR, and EXCLUSIVE OR.

A A
AND C=A·B NAND C = A⋅ B
B B

A A
NOR C = A+ B
OR C=A+B B
B

A
A A C= A⊕ B
B
NOT
EXCLUSIVE OR
12/8/2004 EE 42 fall 2004 lecture 41 16
 Evaluation of Logical Expressions with “Truth Tables”

The Truth Table completely describes a logic expression

In fact, we will use the Truth Table as the fundamental

meaning of a logic expression.
Two logic expressions are equal if their truth tables are the
same

12/8/2004 EE 42 fall 2004 lecture 41 17

 Some Useful Theorems
1) A • B = B • A
Communicative Defined from form
2) A + B = B + A of truth tables
3) A + B + C = C + B + A
Associative
4) A • B • C = C • B • A
5) A • A = 0
6) A + A = 1 Each of these can be
proved by writing out
7) A • B + A • C = A • (B +Distributive
C)
truth tables
8) A • B = A + B
9) A + B = A • B
} de Morgan’s Laws
12/8/2004 EE 42 fall 2004 lecture 41 18
 Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS. If we may use De Morgan’s theorem we
may turn the sum-of-products expression into a form directly implementable
entirely with NAND gates. (We also need the NOT function, but that is
accomplished by a one-input NAND gate). function.
Starting with any SUM-OF-PRODUCTS expression:
Y = ABC+DEF we can rewrite it by “inverting” with De Morgan:
Y = [ (ABC) • (DEF)] Clearly this expression is realized with three NAND
gates: one three-input NAND for (ABC) , one for
A (DEF) , and one two-input gate to combine them:
B
C
Y The NAND realization, while based on
D DeMorgan’s theorem, is in fact much
E simpler: just look at the sum of products
F
expression and use one NAND for each term
and one to combine the terms.

12/8/2004 EE 42 fall 2004 lecture 41 19

 Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS (CONTINUED).

Two Examples of SUM-OF-PRODUCTS expressions:

X = AB + AB (X-OR function) Y = ABC + AB C
A B C
A

X Y

B
(No connection)
We could make the drawings simpler
by just using a circle for the NOT
function rather than showing a one-
input NAND gate
12/8/2004 EE 42 fall 2004 lecture 41 20
 Controlled Switch Model of Inverter
- VDD = 3V Note top, type
SP is closed if VIN P, switch is
SP < VDD by 2V
+ “upside down”
RP
VIN VOUT
+
+
Input RN
+SN is closed if Output
- SN VIN > VSS by 2V -
-
VSS = 0V

The idea: If input is 3V then top switch open, bottom one closed. And
if input is 0V, bottom switch is open, and top switch closed. Thus we
connect the output (through one of the resistors RP or RN) to either
ground or VDD .
12/8/2004 EE 42 fall 2004 lecture 41 21
 CMOS
Both NMOS and PMOS on a single silicon chip

NMOS needs a p-type substrate

PMOS needs an n-type substrate

But we can build in the same substrate by changing doping

type
G D D G
S S
oxide
p p n n
n-well p-well

We can butt the p and n together, or even let, for example

the entire non n-wellEE
12/8/2004 region be lecture
42 fall 2004 p type.41 22
 Basic CMOS Inverter

Inverter CMOS VDD

VDD Inverter
IN p-ch

IN OUT OUT

n-ch

Al “wires” VDD

IN PMOS Gate
Example layout of
N-WELL CMOS Inverter
OUT

NMOS Gate

GROUND
12/8/2004 EE 42 fall 2004 lecture 41 23
 Al “wires” VDD

IN PMOS Gate

N-WELL

OUT

NMOS Gate

GROUND

12/8/2004 EE 42 fall 2004 lecture 41 24

 NMOS TransistorV
DS

- +

VGS drain
gate
- + ID
IG
source
metal
metal oxide insulator metal
n-type n-type

p-type

metal
+ G
IG
V
GS
_ ID
S D
- VDS +
12/8/2004 EE 42 fall 2004 lecture 41 25
 NMOS I-V Characteristic
G
+ IG
V
_ GS ID

S D
- VDS +

• Since the transistor is a 3-terminal device, there is no

single I-V characteristic.
• Note that because of the insulator, IG = 0 A.
• We typically define the MOS I-V characteristic as
ID vs. VDS for a fixed VGS .
• The I-V characteristic changes as VGS changes.
12/8/2004 EE 42 fall 2004 lecture 41 26
 NMOS I-V Curves
ID triode mode saturation mode

VGS = 3 V

VDS = VGS - VTH(n)

VGS = 2 V

VGS = 1 V

VDS
cutoff mode (when VGS < VTH(N) )
12/8/2004 EE 42 fall 2004 lecture 41 27
 Saturation in a MOS transistor
• At low Source to drain voltages, a MOS transistor looks
like a resistor which is “turned on” by the gate voltage
• If a more voltage is applied to the drain to pull more
current through, the amount of current which flows stops
increasing→ an effect called pinch-off.
• Think of water being sucked through a flexible wall tube.
Dropping the pressure at the end in order to try to get
more water to come through just collapses the tube.
• The current flow then just depends on the flow at the
input: VGS
• This is often the desired operating range for a MOS
transistor (in a linear circuit), as it gives a current source
at the drain as a function of the voltage from the gate to
the source.

12/8/2004 EE 42 fall 2004 lecture 41 28