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Converting among Representations

Can convert from any representation Inputs Outputs Term


to any other a b F F = sum of
0 0 1 ab
Common conversions 0 1 1 ab
Equation to circuit (we did this earlier) 1 0 0
1 1 0
Truth table to equation (which we can
convert to circuit) F = ab + ab
Easy -- just OR each input term that
should output 1
Q: Convert to equation
Equation to truth table
a b c F
Easy -- just evaluate equation for each 0 0 0 0
input combination (row) 0 0 1 0
Creating intermediate columns helps 0 1 0 0
0 1 1 0
Q: Convert to truth table: F = ab + ab 1 0 0 0
Inputs Output 1 0 1 1 abc
1 1 0 1 abc
a b a' b' a' b F
a
1 1 1 1 abc a
0 0 1 0 1
0 1 0 1 1 F = abc + abc + abc
1 0 0 0 0
Digital Design
Copyright 2006 1 1 0 0 0
1
Frank Vahid
Decoder Example
New Years Eve 210 21 0 0
Happy
0 1 0 0 0 1 New Year
Countdown Display 1 0 0
i0 d0
0 1 0
i1 d1 1
Microprocessor counts 0 0 0 i2 d2 1 0 0 2
0 0 0 i3 d3 0 0 0 3
from 59 down to 0 in essor a

binary on 6-bit output


co
0
r
0 0 i4
0 0 0 i5
o
ricp d58 0 0 0
Want illuminate one of 60 M e d59 0 0 0
lights for each binary d60
d61 58
number 6x64 d62 59
Use 6x64 decoder dcd d63

4 outputs unused

Digital Design
Copyright 2006 2
Frank Vahid
Controller Design: Laser Timer Example
Step 1: Capture the FSM Inputs: b; Outputs: x
x=0
Already done 00
Off b
Step 2: Create architecture a

b
2-bit state register (for 4 states) x=1 x=1 x=1

Input b, output x 01 On1 10 On2 11 On3

Next state signals n1, n0


Step 3: Encode the states outpu

outputs
inputs
FSM
b x

FSM
Combinational n1
FSM
Any encoding with each state logic
unique will work n0
a
s1 s0

clk State register

Digital Design
Copyright 2006 3
Frank Vahid
Controller Design: Laser Timer Example (cont)
Step 4: Create state table Inputs: b; Outputs: x
x=0
00
Off b
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3

outputs
inputs
FSM

FSM
b x
Combinational n1
logic
n0
s1 s0
clk State register

Digital Design
Copyright 2006 4
Frank Vahid
Controller Design: Laser Timer Example (cont)
Step 5: Implement

outputs
inputs
FSM

FSM
b x
combinational logic Combinational n1
logic
n0
a
s1 s0
clk State register

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0


= 1)

n1 = s1s0b + s1s0b + s1s0b + s1s0b


n1 = s1s0 + s1s0

n0 = s1s0b + s1s0b + s1s0b


n0 = s1s0b + s1s0

Digital Design
Copyright 2006 5
Frank Vahid
Controller Design: Laser Timer Example (cont)
Step 5: Implement b
Combinational Logic
x FSM ou

outputs
inputs
combinational logic (cont)

FSM

FSM
b x
Combinational n1
FSM inputs logic n1 a
n0
s1 s0
clk State register
n0

s1 s0

clk State register

x = s1 + s0
n1 = s1s0 + s1s0
n0 = s1s0b + s1s0

Digital Design
Copyright 2006 6
Frank Vahid
Register Example using the Load Input:
Weight Sampler
Scale has two displays
Present weight
Saved weight Scale Weight Sampler

Useful to compare 0 0 1 01
present item with previous
item Save
3 pounds
2
b 1 load
I3 I2 I1 I0 a

Use register to store clk


0011
Present weight Q3 Q2 Q1 Q0
weight
Pressing button causes
present weight to be 3 pounds
stored in register Saved weight
Register contents
always displayed as
Saved weight, even
when new present
weight appears
Digital Design
Copyright 2006 7
Frank Vahid
Carry-Ripple Adders Behavior
000 10 0 101 1 1
0 0111+0001
(answer should be 01000)
a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
0 1 1
co1 Outputs after 4ns (2 FA delays)
0 0 1 0 0
(b)
000 101
0 101 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1 a
co2 Outputs after 6ns (3 FA delays)
0 0 0 0 0
(c)
0 00
1 10 1 101 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1
0 1 0 0 0 Output after 8ns (4 FA delays)
Digital Design (d)
Copyright 2006 Correct answer appears after 4 FA delays 8
Frank Vahid
Magnitude Comparator
How does it 1011 = 1001 ?
1 = 1 0 0 1 0 1 1
work? a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq=1 causes this 1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
stage to compare Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0


(a)
a

1 1 0 = 0 1 0 1 1
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0


Digital Design (b)
Copyright 2006 9
Frank Vahid
Magnitude Comparator
1 1 0 0 1 > 0 1 1
1011 = 1001 ? a3 b3 a2 b2 a1 b1 a0 b0 Final answer
appears on the
a b a b a b a b right
0 1
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB Takes time for
1 0
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0 answer to
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB
ripple from left
Stage3 Stage2 Stage1 Stage0 to right
(c) Thus called
a 1 1 0 0 1 0 1 1 carry-ripple
a3 b3 a2 b2 a1 b1 a0 b0 style after the
carry-ripple
a b a b a b a b adder
0 1
Igt
1
in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt
0
AgtB Even though
Ieq
0
in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0
theres no
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB carry
involved
Stage3 Stage2 Stage1 Stage0
Digital Design (d)
Copyright 2006 10
Frank Vahid
Counter Example: Light Sequencer
Illuminate 8 lights from right
to left, one at a time, one per 1 cnt 3-bit up-counter
second clk tc c2 c1 c0
Use 3-bit up-counter to (1 Hz)
0 10 010
counter from 0 to 7 unused

Use 3x8 decoder to 3x 8 dcd i2 i1 i0


illuminate appropriate light d7 d6 d5 d4 d3 d2 d1 d0
Note: Used 3-bit counter a

with 3x8 decoder lights


NOT an 8-bit counter why
not?

Digital Design
Copyright 2006 11
Frank Vahid
RTL Example: Bus Interface

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits)


Outputs: D (32 bits)
Local register: Q1 (32 bits) A Faddr Q
rd rd
4 4 32
((A = Faddr)
and rd) Q1_ld
ld Q1
WaitMyAddress SendData
(A = Faddr)
D = Z and rd D = Q1 = (4-bit)
Q1 = Q 32
A_eq_Faddr

D_en
32
a

Step 2: Create a datapath Datapath


(a) Datapath inputs/outputs Bus interface
(b) Instantiate declared registers D
(c) Instantiate datapath components and
connections
Digital Design
Copyright 2006 12
Frank Vahid
State Reduction Example
Given FSM on the right Inputs: x; Outputs: y

x x x x x
Step 1: Mark state pairs having
x x x
different outputs as nonequivalent S0 S1 S2 S3
y=0 y=1 y=1 y=1

S1

S2 a

S3

S0 S1 S2

Digital Design
Copyright 2006 13
Frank Vahid
State Reduction Example
Given FSM on the right Inputs: x; Outputs:
Outputs: yy

x x x x x
Step 1: Mark state pairs having
x x x
different outputs as nonequivalent S0 S1 S2 S3

Step 2: For each unmarked state y=0 y=1 y=1 y=1

pair, write the next state pairs for the


same input values S1
x=0
(S2, S2) x=1
S2 (S3, S1)
a

(S0, S2) (S0, S2)


S3 (S3, S1) (S3, S3)

S0 S1 S2

Digital Design
Copyright 2006 14
Frank Vahid
State Encoding: One-Hot Encoding
Inputs: none; Outputs: x
One-hot encoding x=0 x=1

One bit per state a bit being 1 A 00


0001
D 11
1000
corresponds to a particular state
Alternative to minimum bit-width
encoding in previous example B 01 C 10
0010 0100 a
For A, B, C, D: A: 0001, B: 0010, C: x=1 x=1

0100, D: 1000
Example: FSM that outputs 0, 1, 1, 1
Equations if one-hot encoding:
n3 = s2; n2 = s1; n1 = s0; x = s3 +
s2 + s1
Fewer gates and only one level of x
x

logic less delay than two levels, so


faster clock frequency
n1
8
binary s3 s2 s1 s0
6 n0
s1 s0
4 one-hot clk State register
clk State register
2 n0
Digital Design n1
n2
n3
Copyright 2006 1 2 3 4 15
Frank Vahid delay (gate-delays)