Introduction to VLSI

Circuits
Naveen Bhat,
Teaching assistant
Karnatak university,
dharwad
Tale of two queries. !!!!

Y U R here..?

Y I M here. ?
Acknowledgement
This lecture note has been summarized from
lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I cant
remember where those slide come from.
However, Id like to thank all professors who
create such a good work on those lecture notes.
Without those lectures, this slide cant be
finished.
Major source of this presentation is based on
thecource of Dept. of Electronic Engineering
National Chin-Yi University of Technology
 Bibliography
Textbook

Introduction to VLSI
Circuits and Systems,
by John P. Uyemura
Referrence book
Principles of CMOS
VLSI Design,
N.H.E. Weste and K.
Eshraghian
pre-requistics:
Course prerequistics:
Construction and working of BJT.

Construction and working of FET(MOSFET).

Concept of logic gates.

Ideal switches and boolean expressions.

5 October 26, 2017

VLSI Overview
VLSI:very large scale integrated circuits.

Why Make IC

IC Evolution

Common technologies

6 October 26, 2017

 Why Make ICs
Integration improves
size
speed
Power

Integration reduce manufacturing costs

(almost) no manual assembly

7 October 26, 2017 \

 IC Evolution (1/3)
SSI Small Scale Integration (early 1970s)
contained 1 10 logic gates

MSI Medium Scale Integration

logic functions, counters

LSI Large Scale Integration

first microprocessors on the chip

VLSI Very Large Scale Integration

now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2),
floating-point arithmetic unit(s), etc.
8 October 26, 2017
 IC Evolution (2/3)
Bipolar technology
TTL(transistor-transistor logic)
ECL (emitter-coupled logic)

MOS (Metal-oxide-silicon)
although invented before bipolar transistor,
was initially difficult to manufacture
nMOS (n-channel MOS) technology developed in
1970s
required fewer masking steps, was denser, and
consumed less power than equivalent bipolar ICs =>
an MOS IC was cheaper than a bipolar IC and led to
investment and growth of the MOS IC market.
9
IC Evolution (3/3)
aluminum gates for replaced by polysilicon by early
1980
CMOS (Complementary MOS): n-channel and p-
channel MOS transistors =>
lower power consumption, simplified fabrication
process
Bi-CMOS - hybrid Bipolar, CMOS (for high
speed)
GaAs - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germanium (for RF)

10 October 26, 2017

Outline
Complexity and Design
Basic Concepts
 Complexity and Design
Creating a design team provides a realistic
approach to approaching a VLSI project, as it
allows each person to study small sections of
the system
Needing hundreds of engineers,
scientists, and technicians.
Needing hierarchy design and many
different Level Views.
Everyone of each level depends upon the
Computer-Aided Design (CAD) tools.

Figure 1.1 The VLSI design funnel

Design Hierarchy (1/2)
System specifications: is defined in both
general and specific terms, such as
functions, speed, size, etc.

Abstract high-level model: contains

information on the behavior of each block
and the interaction among the blocks in the
system

Logic synthesis: To provide the logic design

of the network by specifying the primitive
gates and units needed to build each unit

Circuit design: where transistors are used as

switches and Boolean variables are treated
as vary voltage signals

Physical design: the network is built on a tiny

area on a slice of silicon

Figure 1.2 General overview

Manufacturing: a completed design process of the design hierarchy
is moved on to the manufacturing line
 Design Hierarchy (2/2)
Hierarchical design:
Top-down design
the initial work is quite abstract and
theoretical and there is no direct
connection to silicon until many steps
have been completed
Acceptable in modern digital system
design
Co-design with combining HW/SW is
critical

Bottom-up design
starts at the silicon or circuit level and
builds primitive units such as logic
gates, adders, and registers as the
first steps
Acceptable for small projects

A simple design flow for a

microprocessor
VLSI Chip Types
At the engineering level, digital VLSI chips are classified by the approach
used to implement and build the circuit
Full-custom Design:
where every circuit is custom designed for the project
Extremely tedious

Time-consuming process

Application-Specific Integrated Circuits (ASICs):

using an extensive suite of CAD tools that portray the system design in
terms of standard digital logic constructs
Including state diagrams, functions tables, and logic diagram

Designer does not need any knowledge of the underlying electronics

or the physic of the silicon chip
Major drawback is that all characteristics are set by the architectural
design
Semi-custom Design:
between that of a full-custom and ASICs
Using a group of primitive predefined cells as building blocks, called
cell library.
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
p-n Junction
A junction between p-type and n-type
semiconductor forms a diode
Current flows only in one direction

anode cathode

N
 nMOS Transistor
Four terminals: gate (G), source (S), drain (D), body (B)
Gateoxidebody stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
Even though gate is no longer made of metal
 nMOS Operation (1/2)
Body is usually tied to ground (0 V)
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
nMOS Operation (2/2)
When the gate is at a high voltage
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon
from source through channel to drain,
transistor is ON
 pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
 Ideal Switches (1/3)
CMOS integrated circuits use bi-directional devices called MOSFETs as logic
switches
Controlled switches, e.g, assert-high and assert-low switches

An assert-high switch is showing in Figure 2.1

(a) Open (b) Closed

Figure 2.1 Behavior of an assert-high switch

 Ideal Switches (2/3)

g = (a1) b = (a1) b

Figure 2.2 Series-connected switches

g = (a1) + (b1) = a + b

Figure 2.4 Parallel-connected switches

Ideal Switches (3/3)

Figure 2.6 Series-connected complementary switches

(a) Closed

(b) Open

Figure 2.8 A MUX-based

Figure 2.5 An assert-low switch Figure 2.7 An assert-low switch NOT gate
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
 MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect
Transistor

nFET: an n-channel MOSFET that uses negatively

charged electrons for electrical current flow

pFET: a p-channel MOSFET that uses positive (a) nFET symbol

charges for current flow

In many ways, MOSFETs behave like the idealized

switches introduced in the previous section

The voltage applied to the gate determines the

current flow between the source and drain terminals
(b) pFET symbol

Figure 2.9 Symbols used

for nFETs and pFETs
CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

Fabrication and Layout Slide 28

CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

Fabrication and Layout Slide 29

CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

Fabrication and Layout Slide 30

CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

Fabrication and Layout Slide 31

CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

Fabrication and Layout Slide 32

CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

Fabrication and Layout Slide 33

 nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage VTn
that is positive, typical is around VTn = 0.5 V to 0.7 V

If VGSn VTn, then the transistor acts like an open (off)

circuit and there is no current flow between the drain
and source

If VGSn VTn , then the nFET drain and source are (a) Gate-source voltage

connected and the equivalent switch is closed (on)

Thus, to define the voltage VA that is associated with

the binary variable A`

V A VGSn
(b) Logic translation

Figure 2.14 Threshold voltage of an nFET

 pMOS FET Threshold Voltages
An pFET is characterized by a threshold voltage VTp
that is negative, typical is around VTp = 0.5 V to 0.8 V

If VSGp VTp , then the transistor acts like an open

(off) switch and there is no current flow between
the drain and source

If VSGp VTp , then the pFET drain and source are (a) Source-gate voltage
connected and the equivalent switch is closed (on)

Thus, to the applied voltage VA we first sum voltage to

write

V A VSGp VDD
V A VDD VSGp
(b) Logic translation

VDD VTp Figure 2.15 pFET threshold voltage

Note that the transition between a
logic 0 and a logic 1 is at (2.25) !
 nFET Pass Characteristics
An ideal electrical switch can pass any voltage applied
to it

As Figure 2.16(b), the output voltage Vy is reduced to a

value

V1 VDD VTn (2.27) since VGSn VTn

(a) Logic 0 transfer

Which is less than the input voltage VDD, called

threshold voltage loss

Thus, we say that the nFET can only pass a weak logic
1; in other word, the nFET is said to pass a strong logic
0 can pass a voltage in the range [0, V1]

(b) Logic 1 transfer

Figure 2.16 nFET pass characteristics

pFET Pass Characteristics
Figure 2.17(a) portrays the case where Vx = VDD
corresponding to a logic 1 input. The output
voltage is

V y VDD , which is an ideal logic 1 level

Figure 2.17(b), the transmitted voltage can only
drop to a minimum value of
(a) Logic 0 transfer
V y VTp
The results of the above discussion
nFETs pass strong logic 0 voltages, but weak
logic 1 values
pFETs pass strong logic 1 voltages, but weak
logic 0 levels
Use pFETs to pass logic 1 voltages of VDD
Use nFETs to pass logic 0 voltages of VSS = 0 (b) Logic 1 transfer
V Figure 2.17 pFET pass characteristics
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Lay out pattern: (NOT)
Lay out pattern: (NAND)

Y
A
B
Lay out pattern: (NOR)

A
B
Y
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Complex Logic Gate (1/3)
Complex or combinational logic gates
Usefulin VLSI system-level design
Consider a Boolean expression

F (a, b, c) a (b c)

F (a, b, c) a (b c)
a (b c)
[a (b c)] 1

F a 1 (b c) 1
Expanding by simply ANDing the result with a
logical 1
Complex Logic Gate (2/3)
nFET array that
gives F=0 when
necessary

Figure 2.37 Logic function example Figure 2.39 nFET circuit for F

F a 1 (b c) 1
Figure 2.40 Karnaugh for nFET circuit
Figure 2.38 pFET circuit for F
function from equation (2.51)
Structured Logic Design (1/4)
CMOS logic gates are intrinsically
inverting
Output always produces a NOT operation
acting on the input variables

Figure 2.42 Origin of the inverting

characteristic of CMOS gates
Structured Logic Design (2/4)

(a) Series-connected nFETs Figure 2.44 nFET AOI circuit

(b) Parallel-connected nFETs

Figure 2.45 nFET OAI circuit
Figure 2.43 nFET logic formation
Structured Logic Design (3/4)

(a) Parallel-connected pFETs

(a) pFET AOI circuit

(b) pFET OAI circuit

(b) Series-connected pFETs
Figure 2.47 pFET arrays for AOI and OAI gates
Figure 2.46 pFET logic formation
Structured Logic Design (4/4)

(a) AOI circuit (b) OAI circuit

Figure 2.48 Complete CMOS AOI and OAI circuits

Bubble Pushing

(a) NAND - OR
(a) Parallel-connected pFETs

(b) NOR - AND

Figure 2.52 Bubble pushing using DeMorgan rules

(b) Series-connected pFETs

Figure 2.51 Assert-low models for pFETs

XOR and XNOR Gates
An important
example of using
an AOI
a b ab ab
circuit is
(2.71)
constructing
a b ab ab (2.72)
Exclusive-OR
a b (a b) a b a b (2.73)
(a) Exclusive-OR (b) Exclusive-NOR
(XOR)
a b a b a b
and
(2.74) Figure 2.57 AOI XOR and XNOR gates

Exclusive-NOR
circuits
(a) AOI22 (b) AOI321 (c) AOI221

Figure 2.58 General naming convention

Figure 2.56 XOR

Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Transmission Gate Circuits
A CMOS TG is created by connecting an
nFET and pFET in parallel
Bi-directional y x s iff s 1
Transmit the entire voltage range [0, VDD]

Figure 2.60 Transmission gate (TG)

XOR GATE:
Logic Design using TG (1/3)
Multiplexors F P0 s P1 s

TG based 2-to-1 multiplexor

A TG-based 2-to-1 multiplexor

4:1 MUX
Logic Design using TG (2/3)

TG based XOR/XNOR

ab ab a b a b a b a b a b
(2.81) (2.82)

(a) XOR circuit (b) XNOR circuit

TG based OR gate

Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits

f a (a) a b
a a b (2.83)

ab

Figure 2.63 A TG-based OR gate

Logic Design using TG (3/3)

Alternate XOR/XNOR Circuits

Mixing TGs and FETs which are designed for exclusive-OR and
equivalence (XNOR) functions
Its important in adders and error detection/correction algorithms

Figure 2.64 An XNOR gate that used

both TGs and FETs
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Clock and Dataflow Control
Synchronous digital design using a clock
signal
Simply, the switching characteristics of TGs
1
f (2.84)
T

(a) Closed switch

Figure 2.65 Complementary clocking signals

As Figure 2.66(b), when TG is off, the value of y = (b) Open switch

x for a very short time thold. If we use a high-
frequency clock then the periodic open-closed Figure 2.66 Behavior of a clocked TG
change occurs atevery t hold
(T / 2)half clock cycle
Clock and Dataflow Control Using TGs
Data Synchronization
using transmission
gates
To use clocked TGs for
data flow control, we Figure 2.68 Block-level system timing diagram

place oppositely phased

In this scheme, data moves through a
TGs at the inputs and logic block every half cycle
Since the logic blocks are arbitrary, it
outputs of logic blocks can be used as the basis for building
very complex logic chains
Synchronize the operations performed
on each bit of an n-bit binary word

Figure 2.67 Data synchronization using transmission gates

A Synchronized Word Adder
In figure 2.69(a), the input word an-1a0 and bn-1b0 are controlled
by the plane, while the sum sn-1s0 is transferred to the
output when clock
Every bit in a word is transmitted from one point to another at
the same time, which allows us to track the data flow through
the system 0

In figure 2.69(b), a larger scale with the ALU (arithmetic and logic
unit)
Input A and B are gated into the ALU by the control signal
The result word Out is transferred to the next stage when (a) Clocked adder
, i.e.,

plane

1 0
(b) Clocked ALU

Figure 2.69 Control of binary

words using clocking planes
Clock and Dataflow Control
Clocked transmission gates synchronize the flow of signals, but the line
themselves cannot store the values for times longer than thold

(a) Logic diagram (a) Logic diagram

(b) CMOS circuit (b) CMOS circuit

Figure 2.70 SR latch Figure 2.71 Clocked SR latch

Few definations:
Substrate:
Silicon platform on which circuitrary is devoloped.

Photolithography:
Process of transferring pattern on mask to photoresist layer on wafer surface
(pre-pattern the chip)

Etching
Process of permanently removed the unwanted part of design on wafer surface
to get the desired pattern

Diffusion
Process of introducing dophant layer by movement of dophant atoms from high
concentration to low concentration area at high temperature

Ion implantation
Process of introducing dophant layer by bombardment of high energy dophant
ion in high electric field chamber

Oxidation
Process of growing thick or thin SiO2 layer depend on oxide application
 Few concepts:
Fabrication yield:
defect density:
lateral doping:
Beading effect:
Eulers graph:
Single CrystalGrowth
Pure silicon is melted in a pot (1400 C) and a small
seed containing the desired crystal orientation is
inserted into molten silicon and slowly(1mm/minute)
pulled out.
FABRICATION YIELD:

DEFECT DENSITY:
 Overview of silicon processing
material growth and deposition
Lithography
The CMOS process flow
Design rules.
 Material growth:

An integrated ckt is created by stacking layers of

various materials in a pre specified sequence.
Most layers are created first, and then patterned
using the lithographic sequence.
Silicon dioxide:

It is an excellent electrical insulator.

It adheres well to most materials.

It can be grown on a silicon wafer or deposited on top

of the wafer.
 There are 2 types of sio2 layers found in VLSI
ckts, with distinction how they are created.
- thermal oxide
- wet oxidation

Thermal Oxidation:
A thermal oxidation layer is formed by the
reaction
CHEMICAL VAPOUR DEPOSITION:
 Silicon Nitride (Si3N4)
Often called nitride only

Strong barrier to most items

Use as an overglass layer to protect chip

3SiH4 (gas) + 4NH3 (gas) Si3N4 (solid )

+12H2(gas)

Silane Ammonia Silicon Nitride

Polysilicon Silicon:
Depositing silicon on Silicon Dioxide produces small crystallites
areas

Called poly for short

Used for gate eletrotrode in FETs

Metals:
CMOS FABRICATION:
4 different approaches:
N-well proces
P-well process
Twin- well (tub) process
Silicon on insulator (SOI) prcoess
P-well process:
P-well process(cont.)
Cmos inverter:
N-well process:
Twin tub proces:
Silicon-on-insulator:
Physical Design
What is physical design?
To translating logic circuits into silicon.
Switch speed is critical.
The electrical characteristics of a logic gate depend on the aspect ratios
of the transistors
In other words, this is due to both the current flow levels and the parasitic
resistance and capacitance

Layout can be very time consuming.

Design gates to fit together nicely
Build a library of standard cells

Standard cell design methodology.

VDD and GND should be of standard height
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
CAD TOOLSETS
lay out editor:
Graphical interface to data base that allows the user to draw transistors and
wire patterns made up of polygon shape

Extraction routine:
Translates the polygon patterns and layers into its equivalent electrical
networks.
SPICE is used to simulate the network.

LVS:
LAYOUT VERSUS SCHEMATIC.
used to verify the lay out against a schematic diagram.

DRC:
DESIGN RULE CHECKER.
Uses a layout database and checks, to ensure that minimum specified values
are not violated.

PLACE AND ROUTE:

Helps the designer by automatically finding viable wiring routes between two points.

ERC:
Electrical rule checker
Checks electrical continuity.