UNIT - IV

Synchronous Sequential Circuits,

Latches, Flip-flops,
Analysis of clocked sequential circuits,
Registers, Shift registers,
Ripple counters, Synchronous counters, other counters.
Asynchronous Sequential Circuits -Introduction,
Analysis procedure,
Circuits with latches, Design procedure, N Srikanth Prasad
Assistant Professor
Reduction of state and follow tables,
Department of ECE
Race- free state assignment, +91-93 9104 9134
Hazards. nskprasad9@gmail.com
SEQUENTIAL CIRCUITS

The block diagram demonstrates that the outputs in a sequential circuit

are a function not only of the inputs, but also of the present state of the
storage elements.
The next state of the storage elements is also a function of external inputs
and the present state. Thus, a sequential circuit is specified by a time
sequence of inputs , outputs, and internal states. In contrast, the outputs
of combinational logic depend only on the present values of the inputs.
There are two main types of sequential circuits, and their classification is
a function of the timing of their signals.
A synchronous sequential circuit is a system whose behavior
can be defined from the knowledge of its signals at discrete instants of
time.
The behavior of an asynchronous sequential circuit depends upon the
input signals at any instant of time and the order in which the inputs
change.

A synchronous sequential circuit employs signals that affect the storage

elements at only discrete instants of time. Synchronization is achieved by
a timing device called a clock generator, which provides a clock signal
having the form of a periodic train of clock pulses.
The clock signal is commonly denoted by the identifiers clock and clk.
 Synchronous clocked sequential circuit

The storage elements (memory) used in clocked sequential circuits

are called flip flops. A flip-flop is a binary storage device capable of
storing one bit of information.
In a stable state, the output of a flip-flop is either 0 or 1.
STORAGE ELEMENTS: LATCHES

A storage element in a digital circuit can maintain a binary state

indefinitely (as long as power is delivered to the circuit), until
directed by an input signal to switch states.

Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches; those controlled by a clock
transition are flip-flops .
Latches are said to be level sensitive devices;
flip-flops are edge-sensitive devices.

The two types of storage elements are related because latches are the
basic circuits from which all flip-flops are constructed.
SR Latch
 Clocked S-R Flip-Flop
The S and R inputs are synchronous control inputs, which control
the state the FF will go to when the clock pulse occurs.
The CLK input is the trigger input that causes the
FF to change states according to the S and R inputs.
SET-RESET (or SET-CLEAR) FF will change states at positive-
or negative-going clock edges.
 Clocked S-R Flip-Flop
A clocked S-R flip-flop triggered by the
positive-going edge of the clock signal.

The S and R inputs control the state of the FF in the same manner as
described earlier for the NOR gate latch, but the FF does not respond
to these inputs until the occurrence of the PGT of the clock signal.
 Clocked S-R Flip-Flop

Waveforms of
the operation of
a clocked S-R
flip-flop triggered
by the positive-
going edge of a
clock pulse.
Clocked S-R Flip-Flop
A clocked S-R flip-flop triggered by the
negative-going edge of the clock signal.

Both positive-edge and negative-edge

triggering FFs are used in digital systems.
Clocked S-R Flip-Flop Internal Circuitry

An edge-triggered S-R flip-flop circuit features:

A basic NAND gate latch formed by NAND-3 and NAND-4.
A pulse-steering circuit formed by NAND-1 and NAND-2.
An edge-detector circuit.
Characteristic Table of an S-R Flip-flop

The characteristic table of a flip-flop actually gives us an idea about the

character, i.e., the working of the flip-flop.

The characteristic table we have to find out the characteristic

equation of the S-R flip-flop.
 The characteristic equation of the S-R flip-fl op from the characteristic table with the help of
the Karnaugh map
Characteristic Table of a D Flip-flop

The characteristic equation of the D flip-flop from the characteristic

table with the help of the Karnaugh map

The characteristic equation of a D flip-flop is

J-K FLIP-FLOP
Characteristic Table of a J-K Flip-flop
The characteristic equation of the J-K flip-fl op from the
characteristic table with the help of the Karnaugh map

The characteristic equation of a J-K flip-flop is

T FLIP-FLOP
T flip-flop has actually only two states
toggle state and memory state

The truth table of a T flip-flop

Characteristic Table of a T Flip-flop

the characteristic equation of the T flip-flop from the characteristic

table with the help of the Karnaugh map

The characteristic equation of a T flip-flop is

EXCITATION TABLE OF A FLIP-FLOP
The excitation table for S-R, D, J-K, and T flip-flops.
These conditions are derived from the corresponding characteristic
tables of the flip-flops.
Conversion of an S-R Flip-flop to a D Flip-flop
The excitation tables of S-R and D flip-flops are given in the table in
D flip-flop using an S-R flip-flop.
 DESIGN PROCEDURE OF SEQUENTIAL CIRCUITS
The design of a sequential circuit follows certain steps. The steps may be listed as
follows:
1. The word description of a circuit may be given accompanied with a state diagram,
or timing diagram, or other pertinent information.
2. Then from the given state diagram the state table has to be prepared.
3. If the state reduction mechanism is possible, then the number of states may be
reduced.
4. After state reduction, assign binary values to the states if the states contain letter
symbols.
5. Then the number of flip-flops required is to be determined. Each flip-flop is
assigned a letter symbol.
6. Then the choice has to be made regarding the type of flip-flop to be used.
7. With the help of a state table and the flip-flop excitation table the circuit excitation
and the output tables have to be determined.
8. Then using some simplification technique e.g., a Karnaugh map or some other
method, the circuit output functions and the flip-flop input functions have to be
determined.
9. Then the logic diagram has to be drawn.
State Diagram.

To design the clocked sequential circuit whose state diagram is given below.
The state table for the state diagram
The state diagram for the reduced state table consists of only five states
Reduced state table.

Reduced state diagram.

Four possible binary assignments.

Reduced state table with binary assignment 1.

the procedure for obtaining the excitation table and the combinational gate structure.