Lecture 12

Reduced Instruction Set Computers

(RISCs)

Zelalem Birhanu, AAiT 1

 In this lecture:

CISC Architecture
RISC Architecture
CISC Vs. RISC

Zelalem Birhanu, AAiT 2

 CISC Architecture

In the 1970s:
Memory was expensive and slow
Compilers were not efficient (mostly assembly was
written by hand)

Thus a good processor design was a design that:

Allowed use of small memory size
Small number of instructions per program
Made programming (compiling) easy

Zelalem Birhanu, AAiT 3

 CISC Architecturecntd

Therefore the trend at the time was to:

Design processors with complex instructions

A single instruction performs many operations (An
instruction resembles a command in a high level
language)
Emphasis is given to hardware than software
(complex instructions => complex hardware)

Such microprocessors are later to be called Complex

Instruction Set Computers (CISC)
Zelalem Birhanu, AAiT 4
 CISC Architecturecntd

Example: Multiply two numbers. Memory

In high level language (HLL): a
b
a=a*b
a and b are variables (memory locations)
Possible equivalent CISC instruction:
MUL a, b
The HLL command translates to a single
instruction
Easier for a compiler to translate
Little memory required to store such instructions

Zelalem Birhanu, AAiT 5

 CISC Architecturecntd

The MUL instruction fetches data from

memory, performs multiplication and
stores the result in memory (It is a complex
instruction)

This instruction may take multiple clock

cycles to execute

Zelalem Birhanu, AAiT 6

 CISC Architecturecntd

CISC Characteristics
Complex, multi-cycle instructions
Emphasis on hardware
Many addressing modes
Variable length instructions
Tries to improve performance by reducing number
of instructions for a program

Example CISC processors

Intel x86, VAX
Zelalem Birhanu, AAiT 7
 RISC Architecture

In the early 1980s

Some researchers realized that fancy complex
instructions are not utilized most of the time
(inefficient hardware utilization)

Compilers were improving and memory was getting

cheaper

Instead of complex instructions use simple

instructions that execute in a single clock cycle

Such type of processors are termed as Reduced

Instruction Set Computers (RISCs)
Zelalem Birhanu, AAiT 8
 RISC Architecturecntd

Example: Multiply two numbers. Memory

In high level language (HLL): a
a=a*b b

Possible equivalent RISC program:

Registers
LOAD R0, a
R0
LOAD R1, b R1
MULT R0, R1 R2
STOR R0, a
The HLL command translates to four instructions
More work for the compiler
More memory required to store the instructions
Zelalem Birhanu, AAiT 9
 RISC Architecturecntd

Advantages of RISCs
Simple instructions => less complex hardware
(control unit) => room for more registers
(=> faster programs )

All instructions execute in a uniform amount of

time (one clock cycle) => pipelining is easier

Zelalem Birhanu, AAiT 10

 RISC Architecturecntd

RISC Characteristics
Simple, single-cycle instructions
Simple addressing modes
Fixed-length and fixed format instructions
Large number of registers
Emphasis on software
Tries to improve performance by reducing CPI
Memory access using only load and store instructions
(Load/store architecture )

Example RISC processors

ARM, PowerPC
Zelalem Birhanu, AAiT 11
 CISC Vs. RISC (summary)

CISC
Complex instructions,
require multiple cycles
Small code size
Many instructions can
reference memory
Few general purpose
registers
Emphasis on hardware
RISC
Reduced (simple) instructions,
take 1 cycle
Large code size
Only Load and Store
instructions can reference
memory
Many general purpose
registers
Emphasis on software

A processor doesnt have to be purely CISC or purely RISC, it can

take good features from both types
Zelalem Birhanu, AAiT 12
 More Readings

1. http://www-cs-
faculty.stanford.edu/~eroberts/courses/soco/
projects/risc/risccisc/

Zelalem Birhanu, AAiT 13