ECE 617 - Fault Testable Design

Dr. Janusz Starzyk

School of EECS
Ohio University
Athens, OH, 45701

http://www.arltesting.com/
Partially based on Prof. Vishwani D. Agrawal lecture VLSI Testing
and book by S. Mourad, Y. Zorian, "Principles of Testing Electronic Systems
IC Testing Machine
(IC81-0444-467)
3360-P VLSI Test System
Definition
of
Testing
Outline 0.18u VLSI silicon neurons
http://www.ini.uzh.ch/node/21083
Reliability and testing
Design Process
Verification & testing
Faults and their detection
Fault coverage
Types of tests
Test applications
Design for Test
Test economics
Reliability and Testing
Reliability of electronics systems is no longer
limited to military, aerospace or banking
Used by almost everyone in the workplace
Applied to smaller and smaller devices
Have continually new failure modes
Reliability depending on being error free
Failures in both software and hardware
Here we concentrate on hardware
Test Objective
The goal over time is to reduce the cost of
manufacturing the product by reducing the per-part
recurring costs:

- reduction of silicon cost by increasing volume and

yield, and by die size reduction (process shrinks or
more efficient layout)

- reduction of packaging cost by increasing volume,

shifting to lower cost packages if possible (e.g., from
ceramic to plastic), or reduction in package pin count
Test Objective
- reduction in cost of test by:
- reducing the vector data size
- reducing the tester sequencing complexity
- reducing the cost of the tester
- reducing test time
- simplifying the test program
A System on a Chip

Interface Block Controller

RAM (RT Level ) (algorithm)

UDL
FPGA UDL
Micropro.
(Layout)
DSP
RAM
(Netlist)
Verification and Testing
Testing a circuit prior to fabrication is known as
design verification
Verification is certainly done at various stages of the
design process
Most viable design verification is through simulation
Testing is identifying that the fabricated circuit is free
from errors
Need to specify what errors testing is looking for
DFT Cycle
Behavioural
Gate
Description

Behavioral T echnology
DFT Mapping
Synt hesis

Layout
RT L Description
Libraries
P arameter
Logic Extract ion
DFT Libraries
Synt hesis
Manufact uring
Gate Description

P roduct
T est P att ern
Generat ion
T est Application

low Fault high Good Product

Coverage?
Test Programming
Types of
Logic
Faults
Types of
Physical
Faults
Faults and their Detection
Physical failures are manifested as electrical
failures and are interpreted as faults on the
logic level
Several physical defects may be mapped into
few fault types
The main fault type is Stuck-at Fault
A fault is detected by a test pattern
Test pattern is an input combination that
confirms the presence of the fault
Possible Defects
R Z
L B

A Z
A R1
A Z
R2 B
A Z

(a) (b)
Two technologies, two physical defects map into the
same stuck-at zero fault
Notation used - A SA0, A@0, or A/0
Detecting Stuck-at Faults
A Fill in the blanks in
Z
B faulty response A/0 and A/1

Inputs FF Faulty Response

AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 1
01 0 0 0 0 1
10 0 0 0 1 1
11 1 0 0 1 1
Detecting Stuck-at Faults

A
Z
B
Inputs FF Fault y Response
AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
Detecting Stuck-at Faults
A
Z
B

Inputs Fault Free Faulty Responses

AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
Sequential Circuit
R
1
A Q

S 2

Inputs FF Faulty Response

SR Response A/0 S/0 R/0 A/1 S/1 R/1
01 0 0 0 X 0 0 1
00 0 1 0 X 1 0 1
10 1 1 0 1 0 1 1
11 0 0 0 1 1 1 1
Types of
Testing
 Types of Tests
The exhaustive test used to detect the faults on a
2-input AND gate is not practical for circuits with
20 or more primary inputs
Pseudo-exhaustive: exhaustive for components in
the circuits
segmentation or partitioning
A random test is also viable to detect faults, but
pseudo-exhaustive tests are more realistic for
Stuck-at Faults
Deterministic or fault oriented tests
 Functional Testing

Exhaustive & pseudo-exhaustive testing :

Partial dependence circuits:

-a circuit in which primary outputs (PO)
depend on all the primary inputs (PI)
- each output tested using 2ni inputs
(ni < n shows inputs affecting PO)
 Functional Testing

Exhaustive & pseudo-exhaustive testing

Example :

Exhaustive test
for each gate
 Functional Testing

Exhaustive & pseudo-exhaustive testing

Partitioning technique :
the circuit is partitioned into segments such that
each segment has small number of inputs
each segment is tested exhaustively
usually inputs & output of each segment are not
PIs or POs so we need to control segment
inputs using PIs and observe its outputs using
PO - this lead to sensitizing partitioning
 Functional Testing

Example : Consider the following circuit :

 Functional Testing

Example: the following shows 8

input vectors to test exhaustively h.
 Functional Testing

Example:
Add vectors 5 - 8 to test exhaustively g
and 9 -10 to test exhaustively y
 Functional Testing

Example:
Add missing combinations to vectors
4 and 9 to test exhaustively x
 Types of Testing
Verification testing, characterization testing
Verifies correctness of design and correctness of
test procedure
May require correction of either or both
Manufacturing testing
Factory testing of all manufactured chips for
parametric and logic faults, and analog
specifications
Burn-in or stress testing
Acceptance testing (incoming inspection)
User (customer) tests purchased parts to ensure
quality
 Verification Test
Very expensive
Applied to selected parts
Used prior to production or manufacturing test
May comprise:
Scanning Electron Microscope tests
Bright-Lite detection of defects
Electron beam testing
Artificial intelligence (expert system) methods
Repeated functional tests
 Manufacturing Test
Determines whether manufactured chip meets
specification
Must cover high % of modeled faults
Must minimize test time (to control cost)
No fault diagnosis
Test at rated speed or at maximum
speed guaranteed by supplier
 Burn-in or Stress Test
Process:
Subject chips to high temperature and over-voltage
supply, while running production tests
Catches infant mortality cases
These are damaged or weak (low reliability) chips that will fail
in the first few days of operation
Burn-in causes bad devices
to fail before they are
shipped to customers
 Manufacturing Test Scenarios
Wafer sort or probe test
Done before wafer is scribed and cut into chips
Test devices are checked with specific patterns to
measure:
Gate threshold
Polysilicon field threshold
Poly sheet resistance, etc.
Packaged device tests
 Types of Tests
Parametric measures electrical properties of pin
electronics delay, voltages, currents, etc. fast and
cheap
Functional used to cover very high % of modeled
faults test every transistor and wire in digital
circuits long and expensive

http://www.ece.unm.edu/~jimp/vlsi/slides/c1_intro-8.gif
 Functional Test
ATE and Manufacturing World any vectors applied
to cover high % of faults during manufacturing test
Automatic Test-Pattern Generation World testing
with verification vectors, which determine whether
hardware matches its specification typically have
low fault coverage (< 70 %)
 Levels of testing

Levels
Chip
Board
System
Boards put together
System-on-Chip (SoC)
System in field Mixed Signal VLSI Circuit
Cost Rule of 10
It costs 10 times more to test a device as we
move to higher levels in the product
manufacturing process
 Levels of testing
Other ways to define levels these are
important to develop correct fault models
and simulation models
Transistor
Gate
RTL
Functional
Behavioral
Architecture
Focus: Chip level testing
gate level design
 Typical Test Program
1. Probe test (wafer sort)
Catches gross defects
2. Contact electrical test
3. Functional & layout-related test
4. DC parametric test
5. AC parametric test
Unacceptable voltage/current/delay at pin
Unacceptable device operation limits
Rise/fall Time Tests
Set-up and Hold Time Tests
 Propagation Delay Tests
1. Apply standard output pin load (RC or RL)
2. Apply input pulse with specific rise/fall
3. Measure propagation delay from input to output
Delay between 5 ns and 40 ns (ok)
Delay outside range (fails)
 On Line Testing
Embedded checkers error detection
Periodic diagnostic programs
Watchdog checkers

Encoded
Circuit Under N Output N
Test
N

P
Checker
 On- vs Off-Chip Testing

High Bandwidt h
High Bandwidt h
Low Bandwidth

Logic Logic

Source/ RAM RAM

sink

Analog Analog

External t est Embedded t est External t est Embedded t est

Off chip test On chip test

 Test Specifications & Plan
Test Specifications:
Functional Characteristics
Type of Device Under Test (DUT)
Physical Constraints package, pin numbers, etc.
Environmental Characteristics power supply,
temperature, humidity, etc.
Reliability acceptance quality level (defects/million),
failure rate, etc.
Test plan generated from specifications
Type of test equipment to use
Types of tests
Fault coverage requirement
 Test Data Analysis

Uses of ATE test data:

Reject bad DUTs
Fabrication process information
Design weakness information
Devices that did not fail are good only if tests
covered 100% of faults
Failure mode analysis (FMA):
Diagnose reasons for device failure, and find
design and process weaknesses
Improve logic and layout design rules
 Cost of Testing
Testers cost over
$1 000 000

VLSI Test System TS600

 Cost of Testing

Design for testability (DFT)

Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost
 Cost of Manufacturing Testing

Example test cost:

0.5-1.0GHz, analog instruments,1024 digital
pins: ATE purchase price
= $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
Good

Bad
PCB for 16 channel pin
card for IC tester
henning-eng.com/pcb800.htm
 Test Economics

Time to Market

Revenues
Loss of
Revenues

Time to
Time in Months
Market T

The life cycle of a product is shorter than its design cycle

Time to market needs to be shorten
Testing is necessary for reliability and for improving yield
 VLSI Defects

Good chips
Faulty chips

Smaller dies
Wafer yield = 78/88 = 0.88

Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55

Clustered defects (VLSI)

Wafer yield = 17/22 = 0.77
Yield and Defect Level

Defect Level
% DPM Y=50% Y=90%
1 10000
5000

0.1 1000
500

0.01 100
50

0.001 10
.01 0.1 1 10 TT%
99.99 99.9 99 90 C%
 Yield

Test transparency
Fault coverage
>
 Multi-site Testing

One ATE tests several (usually identical)

devices at the same time
Both probe and package test
DUT interface board has > 1 sockets
Usually tests 2 or 4 DUTS at a time
Usually test 32 or 64 memory chips at a time
Limits: # instruments available in ATE, type
of handling equipment available for package
 Example VLSI Test Systems

Advantest T3347B 40 MHZ testing speed.

Low-cost Parallel Testing of Accommodates up to 512 I/O pins.
Four High-end MCU and Simultaneous testing of up to four
Testing of Large ASIC devices per station.
ADVANTEST Model T6682 ATE
T6682 ATE Block Diagram
 T6682 ATE Specifications
Uses 0.35 mm VLSI chips in implementation
1024 pin channels
Speed: 250, 500, or 1000 MHz
Timing accuracy: +/- 200 ps
Drive voltage: -2.5 to 6 V
Clock/strobe accuracy: +/- 870 ps
Clock settling resolution: 31.25 ps
Pattern multiplexing: write 2 patterns in one
ATE cycle
Pin multiplexing: use 2 pins to control 1 DUT pin
T6682 Pattern Generation
Sequential pattern generator (SQPG):
stores 16 M vectors of patterns to apply to DUT,
vector width determined by # DUT pins
Algorithmic pattern generator (ALPG):
32 independent address bits,
36 data bits
Scan pattern generator (SCPG)
supports JTAG boundary scan,
greatly reduces test vector memory for full-scan testing
 T6682 Test Data Analysis
Uses of ATE test data:
Reject bad DUTS
Fabrication process information
Design weakness information
Devices that did not fail are good only if tests
covered 100% of faults
Failure mode analysis (FMA)
Diagnoses reasons for device failure
Finds design and process weaknesses
Allows improvement of logic & layout design rules
 T6682 Probe Card
Probe card custom printed circuit board (PCB)
on which DUT is mounted in socket
may contain custom measurement hardware
Probe needles
come down and scratch the pads to stimulate/read pins
Membrane probe for unpackaged wafers
contacts printed on flexible membrane, pulled down
onto wafer with compressed air
LTX FUSION HF ATE
 Specifications
Intended for SOC test
digital, analog, and memory test
supports scan-based test
Modular
can be upgraded with additional instruments
enVision Operating System
maximum 64 M vectors memory storage
1 or 2 test heads per tester, maximum of 1024 digital pins,
1 GHz maximum test rate
Analog instruments:
DSP-based synthesizers, digitizers, time measurement, power test,
radio frequency source and measurement capability (up to 4.3 GHz)
 ADVANTEST Model T2000 ATE
Scalable Architecture

Microsoft Windows 2000

C++(Microsoft Visual Studio Professional)

OTPL(Open Architecture Test System

Programming Language)

Re-configurable Program Structure for test

data and algorithm

T2000 System Software Emulator

Wave Tool (Logic Analyzer, Oscilloscope).

 ADVANTEST T6577

Tests SoC/Mixed-Signal
Devices
Supports for a maximum of
1024 logic and/or I/O channels.
Performs parallel test of up to
32 devices
Supports baseband, DVD read
channel, and jitter test
At-speed test of high-speed
memory interfaces
Test rates of up to 667 Mbps
maximum of eight channels