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L15 Specification of

State Machines
VHDL State Machines
State Machine Basics
VHDL for sequential elements
VHDL for state machines
Example Tail light controller
Example counter
Example gray code counter
Ref: text Unit 10, 17, 20
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State Machine Basics
Mealy machine outputs are a function of current
state and current inputs.
Next State Current Output
State Memory State Logic
Inputs Logic (F/Fs) Outputs
Excitation
(next state)
clk

Mealy Machine

Moore machine outputs are a function of the


current state only. Inputs Next
State
Logic
State Current Output
Memory State
(F/Fs)
Logic
Outputs
Excitation
(next state)
clk

Moore Machine

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State machine design
To implement the state machine have option
to use
Traditional methodology state graph, state
table, state assignment, K-maps, implementation
HDL methodology
HDL description directly from word description
State graph and then the HDL description

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In HDLs need state elements
HDL code for the F/Fs
A simple rising edge D Flip Flop
ARCHITECTURE xxx OF yyy IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk=1 AND clkevent;
state <= next_state;
END PROCESS;
Semantics : Process runs at time 0 and then holds for
clock to have an event (change value) and the new
value is a 1.

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Another Form
This is an alternative to the previous HDL
ARCHITECTURE xxx OF yyy IS
BEGIN
PROCESS (clk)
BEGIN
IF (clk=1 AND clkevent)
THEN state <= next_state;
END IF;
END PROCESS;
Semantics Process runs once at time 0 and then
holds until signal clk has an event. It then executes the
IF statement.

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D F/F with reset
ENTITY dff IS
PORT (clk,reset,din : IN bit; qout : OUT bit);
END dff;

ARCHITECTURE one of dff IS -- Entity had sig clk,reset,din: IN and qout:OUT


-- td_reset and td_in are constants.
BEGIN
PROCESS (clk)
BEGIN
IF (clk=0 AND clkevent) THEN
IF (reset =1) THEN
qout <=0 AFTER td_reset;
ELSE
qout <= din AFTER td_in;
END IF;
END IF;
END PROCESS;
END one;

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More complete D F/F
PROCESS (clk,preset,clear,next_state)
BEGIN -- active low preset and clear
IF (preset = 0) THEN
state <= pr_state; --preset state
ELSIF (clear = 0) THEN
state <= clr_state; --clear state
ELSIF (clk = 1 AND clkevent) THEN --rising edge
state <= next_state;
END IF;
END PROCESS;
Semantics runs once at startup. Then whenever any of the
signals in the sensitivity list change value.
Asynchronous preset has priority over clear and a clock edge.
clear has priority over a clock edge.

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VHDL for finite state machines
Use a process to describe the next state logic, often in
a case statement used for determination of the next
state. Will see this in the example.
Use a process to represent the latching/loading of the
calculated next_state such that it becomes the
current_state. This is the only process that generates
sequential elements (F/Fs). The other processes
represent combinational logic.
Use a third process to represent the generation of the
outputs from the current state and possibly the inputs.
This process will have as its inputs, the current state
and, depending on the type of state machine, the state
machine inputs.
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Notes on VHDL style
The style applies to any HDL VHDL, Verilog,
System C
Documents well
Easily maintainable excellent during development
as changes are easily made
Style maps to physical logic using this style can
predict the number of state elements (~) that should
be produced by synthesis
All three styles on the last slide simulate equally
well, but this style also synthesizes well. Works in
XILINX and Altera tools.
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Example
The T-Bird tail light problem
The turn signal indicator had a light sequence on
each lamp.

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State machine description
State Diagram and Transition Table
Output is associated with state a Moore
machine

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Goal is a HDL description
Often you still start with a state diagram and
state table
Where to start with the code?

As with all HDL start with the interface


WHAT ARE THE INPUTS AND OUTPUTS?

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ENTITY for the controller
Inputs are a signal for HDL code for the
Right turn signal entity
Left turn signal ENTITY t_bird IS
Hazard PORT(rts,lts,haz : IN bit;
Clock clk : IN bit;
Outputs are signals for lc,lb,la : OUT bit;
the taillights ra,rb,rc : OUT bit);
lc, lb, la END t_bird;
rc, rb, ra

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For the tail light controller
Inputs are signals for
Right Turn Signal
Left Turn Signal
Hazard
Clock
Outputs are the signals for the lights
la,lb,la
ra,rb,rc
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The ARCHITECTURE
Will use 3 processes
In declarative region of ARCHITECTURE
will declare the state_type for the states.
ARCHITECTURE state_machine OF t_bird IS
TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3);
SIGNAL state,next_state : state_type;
BEGIN

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1st Process sequential elements
Use a process to specify the sequential elements
Here need only simple D F/Fs
-- Process to specify F/Fs
PROCESS
BEGIN
WAIT UNTIL clk=1 AND clkevent;
state <= next_state;
END PROCESS;
This is the only part of the description that
should result in state elements from synthesis.
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2nd Process next state generation
What is the next state -- Next State Logic Process
given the current state PROCESS (state,lts,rts,haz)
BEGIN
and the value present CASE state IS
WHEN idle =>
on the inputs? IF (haz=1 OR (lts=1 AND rts=1)
THEN next_state <= lr3;
This process can be of ESLIF(haz=0 AND (lts=0 AND rts=1))
THEN next_state <= r1;
considerable size. ELSIF(haz=0 AND (lts=1 AND rts=0))
THEN next_state <= l1;
ELSE
Work well using a case next_state <= idle;
END IF;
statement.

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Next State Process
WHEN l1 =>
Code continued IF (haz = 1) THEN next_state <= lr3;
ELSE next_state <= l2;
END IF;
A separate action for WHEN l2 =>
IF (haz = 1) THEN next_state <= lr3;
each state that based on ELSE next_state <= l3;
END IF;
the inputs directs the WHEN l3 => next_state <= idle;
WHEN r1 =>
IF (haz = 1) THEN next_state <= lr3;
value assigned to ELSE next_state <= r2;
END IF;
next_state. WHEN r2 =>
IF (haz = 1) THEN next_state <= lr3;
ELSE next_state <= r3;
END IF;
WHEN r3 => next_state <= idle;
WHEN lr3 => next_state <= idle;
END CASE;
END PROCESS;

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3rd Process Output signals
-- State Machine Outputs Process
A separate process is PROCESS (state)
BEGIN
CASE state IS
used to generate the WHEN idle =>
lc<=0;lb<=0;la<=0;ra<=0;rb<=0;rc<=0;
WHEN l1 =>
final outputs. lc<=0;lb<=0;la<=1;ra<=0;rb<=0;rc<=0;
WHEN l2 =>
lc<=0;lb<=1;la<=1;ra<=0;rb<=0;rc<=0;
Works great for Moore WHEN l3 =>
lc<=1;lb<=1;la<=1;ra<=0;rb<=0;rc<=0;
WHEN r1 =>
type implementations. lc<=0;lb<=0;la<=0;ra<=1;rb<=0;rc<=0;
WHEN r2 =>
lc<=0;lb<=0;la<=0;ra<=1;rb<=1;rc<=0;
Outputs are directly WHEN r3 =>
lc<=0;lb<=0;la<=0;ra<=1;rb<=1;rc<=1;
assigned to. WHEN lr3 =>
lc<=1;lb<=1;la<=1;ra<=1;rb<=1;rc<=1;
END CASE:
END PROCESS;
END state_machine;

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Complete VHDL code (no output)
-- next state logic
ENTITY t_bird IS PROCESS
PORT(rts,lts,haz, : IN bit; BEGIN
CASE state IS
clk : IN bit; WHEN idle => IF(haz=1 OR (lts=1 AND rts =1) THEN
next_state <= lr3;
lc,lb,la : OUT bit; ELSIF (haz=0 AND (lts=0 AND rts=1) THEN
ra,rb,rc : OUT bit); next_state<=r1;
ELSIF (haz=0 AND (lts=1 AND rts=0) THEN
END t_bird; next_state<=l1;
ELSE next_state <= idle;
ARCHITECTURE state_mach OF t_bird IS END IF:
WHEN l1 => IF (haz=1) THEN next_state <= lr3;
TYPE state_type IS ELSE next_state <= l2;
(idle,l1,l2,l3,r1,r2,r3,lr3); END IF;
WHEN l2 => IF (haz=1) THEN next_state <= lr3;
SIGNAL state,next_state : state_type; ELSE next_state <= l3;
BEGIN END IF;
WHEN l3 => next_state <= idle;
-- Process to specify F/Fs WHEN r1 => IF (haz=1) THEN next_state <= lr3;
ELSE next_state <= r2;
PROCESS END IF;
WHEN r2 => IF (haz=1) THEN next_state <= lr3;
BEGIN ELSE next_state <= r3;
WAIT UNTIL clk=1 AND END IF;
clkevent;

WHEN r3 => next_state <= idle;
WHEN lr3 => next_state <= idle;
state <= next_state; END CASE;
END PROCESS;
END PROCESS;

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Having HDL description
Simulate it in a test suite to verify the design
meets specifications. This is the HDL topic
of verification.
For this course will construct simple
testbenches to do simple check.
HDL code can also be synthesized.

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Results of synthesis
From a Mentor graphics tool (several years
back)

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ENTITY t_bird IS
PORT(clk,lts,rts,haz : IN bit;
lc,lb,la,ra,rb,rc : OUT bit);
END t_bird;

From FPGA tools ARCHITECTURE one OF t_bird IS


TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3);
SIGNAL state,next_state : state_type;
BEGIN
--process for F/F
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;

When done in
END PROCESS;

--next state generation


PROCESS (state,rts,lts,haz)
BEGIN

Quartis ALTERA
CASE state IS
WHEN idle => IF (haz='1' OR (lts='1' AND rts='1')) THEN next_state <= lr3;
ELSIF (haz='0' AND lts='0' AND rts='1') THEN next_state <= r1;
ELSIF (haz='0' AND lts='1' AND rts='0') THEN next_state <= l1;
ELSE next_state <= idle;
END IF;

FPGA tool WHEN l1 => IF (haz='1') THEN next_state <= lr3;


ELSE next_state <= l2;
END IF;
WHEN l2 => IF (haz='1') THEN next_state <= lr3;
ELSE next_state <= l3;
END IF;
WHEN l3 => next_state <= idle;
WHEN r1 => IF (haz='1') THEN next_state <= lr3;
ELSE next_state <= r2;
END IF;
WHEN r2 => IF (haz='1') THEN next_state <= lr3;
ELSE next_state <= r3;
END IF;

Use the state WHEN r3 => next_state <= idle;


WHEN lr3 => next_state <= idle;
END CASE;
END PROCESS;

machine VHDL -- the output process


PROCESS (state)
BEGIN
CASE state IS
WHEN idle => lc<='0'; lb<='0'; la<='0'; ra<='0'; rb<='0'; rc<='0';
WHEN l1 => lc<='0'; lb<='0'; la<='1'; ra<='0'; rb<='0'; rc<='0';

code for synthesis WHEN l2 => lc<='0'; lb<='1'; la<='1'; ra<='0'; rb<='0'; rc<='0';
WHEN l3 => lc<='1'; lb<='1'; la<='1'; ra<='0'; rb<='0'; rc<='0';
WHEN r1 => lc<='0'; lb<='0'; la<='0'; ra<='1'; rb<='0'; rc<='0';
WHEN r2 => lc<='0'; lb<='0'; la<='0'; ra<='1'; rb<='1'; rc<='0';
WHEN r3 => lc<='0'; lb<='0'; la<='0'; ra<='1'; rb<='1'; rc<='1';
WHEN lr3 => lc<='1'; lb<='1'; la<='1'; ra<='1'; rb<='1'; rc<='1';
END CASE;
END PROCESS;
END one;

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FPGA results
From the report
Combination LUTs 15
Dedicated logic registers 8 (did a one hot
encoding)
Total pins 10

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The schematic
Big block for state elements

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The implementation
The one hot state machine state diagram

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Lecture summary
VHDL for state machines
T_bird tail light controller example
VHDL
Synthesis results

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