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YoSys (Open Synthesis Suite)

Instructor:
Dr. Osman Hasan
Presented by:
Salman Farsi 202995
Hafiz Hamza Javaid 205483
Outline

Introduction
Key Features
Advantages
Disadvantages
Small Design Examples
A Major Example
Introduction

YoSys is an Open Source Verilog synthesis tool.


YoSys is the first full-featured open source software for Verilog
HDL synthesis. It supports most of Verilog-2005 and is well tested
with real-world designs from the ASIC and FPGA world. The main
goal of YoSys is the synthesis of Verilog HDL to logically equivalent
netlists.
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: System Level
Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: High Level
Functional implementation of circuit in high-level programming language
(C, C++, SystemC, Matlab, Python, etc.).
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: Behavioral Level
Cycle-accurate description of circuit in hardware description language
(Verilog, VHDL, etc.).
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: Register-Transfer Level (RTL)
List of registers (flip-flops) and logic functions that calculate the next state from the
previous one. Usually a netlist utilizing high-level cells such as adders, multipliers,
multiplexer, etc.
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: Logical Gate Level
Netlist of single-bit registers and basic logic gates (such as AND, OR, NOT, etc)
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: Physical Gate Level
Netlist of cells that actually are available on the target architecture (such as CMOS
gates in an ASIC). Optimized for area, power, and/or speed (static timing or number of
logic levels).
Levels of Abstraction for Digital Circuits

System Level
High Level
Behavioral Level
Register-Transfer Level (RTL)
Logical Gate Level
Physical Gate Level
Switch Level
Definition: Switch Level
Netlist of individual transistors.
Synthesis Views & Levels
YoSys Data Flow

Frontend Passes Backend

Read HDL source Each pass either Used to write


and transform it transforms the the resulting
to RTLIL. RTLIL data or netlist to an
analyzes it (e.g. output file.
evaluate a logic
net with a given
input).

HDL RTL Format Netlist


Key Features

Synthesis of final production designs


Pre-production synthesis (trial runs before investing in other tools)
Conversion of full-featured Verilog to simple Verilog
Conversion of Verilog to other formats (BLIF, BTOR, etc.)
Demonstrating synthesis algorithms (e.g. for educational purposes)
Framework for experimenting with new algorithms
Continuously checking the correctness of Yosys and making sure that
new features do not break old ones is a high priority in Yosys
Advantages of YoSys Open Source HDL
Synthesis
Cost
Availability and Reproducibility
Framework
All-in-one-aspects
Educational Tool

YoSys is open source under the ISC license


Cost

This software is free so anyone have permission to use, copy,


modify and distribute this software for any purpose.

Cost of mask set is very low as compared to the cost of design


tools needed to design the mask layouts.
Availability and Reproducibility

Any researcher who wants to publish its research can use this
tool. Its an open source tool which everyone else can also use. Even
if most of institutes have access to all major commercial tools, you
usually do not have easy access to the version that was used in a
research project a couple of years ago.
YoSys source code can also be use with some new parameters
and you can edit your own data and release it alongside your data.
Framework

Yosys is not only a tool. It is a framework that can be used as


basis for other developments, so researchers and hackers alike do
not need to re-invent the basic functionality.

Extensibility

It is one of Yosys design goals. The term extensibility is a systemic


measure of the ability to extend a system and the level of effort
required to implement the extension.
All-in-one

Because of the framework characteristics of Yosys, an increasing


number of features become available in one tool. Yosys not only can
be used for circuit synthesis but also for formal equivalence
checking and for circuit analysis.

Educational Tool
Other synthesis tools are at times very secretive about
their inner workings. They often are black boxes. Yosys is
very open about its internals and it is easy to observe the
different steps of synthesis.
Disadvantages of YoSys

YoSys does not support time driven synthesis.


Multi-output logic cells are ignored by ABC
Limited support for flip flops with non inverted and inverted
outputs in YoSys.
Complex circuits does not work well with YoSys
Not easily compatible with Windows OS.
Unsupported Verilog Features

Some unsupported Verilog 2005 features


Tri-state logic
The wor/wand wire types
Latched logic (is synthesized as logic with feedback loops)
Some non-synthesizable features that should be ignored in
synthesis are not supported by it.
Some important Yosys commands
read_verilog [options] [filename]
load modules from a Verilog file to current design.
hierarchy [-check] [-top <module>]
In parametric designs, a module might exists in several variations with different
parameter values. This pass looks at all modules in the current design and re-runs the
language frontends for the parametric modules as needed.
proc
This pass calls all the other proc_* passes in the most common order.
this replaces the processes in the design with multiplexers, flip-flops and latches.
fsm
This pass calls all the other fsm_* passes in a useful order. This performs FSM
extraction, optimization and encoding
Synthesis codes
(contd.)
memory
This pass calls all the other memory_* passes in a useful order.
techmap [-map filename] [selection]
This pass implements a very simple technology mapper that replaces cells in the
design with implementations given in form of a Verilog source file.
dfflibmap liberty mycells.lib
Map internal flip-flop cells to the flip-flop cells in the technology library specified
in the given liberty file. This pass may add inverters as needed. Therefore it is
recommended to first run this pass and then map the logic paths to the target technology.
Synthesis codes
(contd.)
abc liberty mycells.lib
This pass uses the ABC tool for technology mapping of yosys's internal gate
library to a target architecture.
write_verilog [filename]
write a Verilog file (code) for the current design (netlist).
this code is in structural format.
Example-1: (up counter)
Verilog Code:
module upcounter (
out , // Output of the counter
enable , // enable for counter
clk , // clock Input
reset // reset Input
);
output [7:0] out;
input enable, clk, reset;
reg [7:0] out;

always @(posedge clk)


if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule
Upcounter
(yosys)
read_verilog upcountetr.v
hierarchy check top counter
proc; opt
fsm; opt
memory; opt
techmap; opt
dfflibmap liberty mycells.lib
abc liberty mycells.lib
write_verilog synth_upcounter.v
hierarchy -check top upcounter
Proc; opt
(upcounter)
Upcounter (final netlist)
Example # 2

4-state mealy machine


Hierarchy
(4-state Mealy machine)
Proc; opt
Fsm; opt
techmap;
(Final netlist)
Major Example:

Single port, single read, single write RAM


hierarchy (SP_SR_SW_RAM)
Proc
Fsm; opt
(RAM)
References:

http://www.github.com
http://www.reddit.com
http://www.asicworld.com
EE881 ASIC Design Methodology Osman Hasan, SEECS, NUST, Islamabad, Pakistan.

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