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State Machine Signaling

Timing Behavior
Glitches/hazards and how to avoid them
FSM Partitioning
What to do when the state machine doesnt fit!
State Machine Signaling
Introducing Idle States (synchronous model)
Four Cycle Signaling (asynchronous model)
Dealing with Asynchronous Inputs
Metastability and synchronization

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Midterm #1 Results
Midterm 1

25

20

15
Number

10

0
38 39 40 41 42 43 44 45 46 47 48 49 50
Score

Mean
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Midterm #2 Results
Mid2 Results

5
Number

0
10 15 20 25 30 35 40 45
Score

-2 SD -1 SD Mean +1 SD +2 SD
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Combined Midterm Results
Midterms

6
Number

0
50 55 60 65 70 75 80 85 90 95
Total Score

-2 SD -1 SD Mean +1 SD +2 SD
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Momentary Changes in Outputs
Can be usefulpulse shaping circuits
Can be a problemincorrect circuit
operation (glitches/hazards)
A B C D
Example: pulse shaping circuit F
A' A = 0
delays matter
in function

D remains high for


three gate delays after F is not always 0
A changes from low to high pulse 3 gate-delays wide

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Oscillatory Behavior
Another pulse shaping circuit +

resistor
A B
open C
switch D

close switch

initially
open switch
undefined

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Hazards/Glitches
Hazards/glitches: unwanted switching at the outputs
Occur when different paths through circuit have different
propagation delays
As in pulse shaping circuits we just analyzed
Dangerous if logic causes an action while output is unstable
May need to guarantee absence of glitches

Usual solutions
1) Wait until signals are stable (by using a clock): preferable
(easiest to design when there is a clock synchronous design)
2) Design hazard-free circuits: sometimes necessary (clock not used
asynchronous design)

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Types of Hazards
Static 1-hazard
Input change causes output to go from 1 to 0 to 1 1 1
0

Static 0-hazard
1
Input change causes output to go from 0 to 1 to 0 0 0

Dynamic hazards
Input change causes a double change 1 1
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 0 0

1 1
0 0
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Static Hazards
Due to a literal and its complement momentarily taking
on the same value
Thru different paths with different delays and reconverging
May cause an output that should have stayed at the
same value to momentarily take on the wrong value
Example:
A
A
S B
F
S

S'
B
F
S'
hazard
static-0 hazard static-1 hazard
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Dynamic Hazards
Due to the same versions of a literal taking on
opposite values
Thru different paths with different delays and reconverging
May cause an output that was to change value to
change 3 times instead of once
Example: A

C
A
F B1
3
2
B B2
1
B3
C
F

hazard
dynamic hazards
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Eliminating Static Hazards
Following 2-level logic function has a hazard, e.g.,
when inputs change from ABCD = 0101 to 1101
A
AB
CD 00 01 11 10 A 1
1 A
1
1
G1 G1
\C \C 1
00 0 0 1 1 1 1 1
G3 F G3 F
\A 0 \A 0
G2 G2
D 0 D 0
01 1 1 1 1 0 0
D ABCD = 110 0 ABCD = 110 1
11 1 1 0 0
No Glitch in this case
C
10 0 0 0 0 This is the fix
B Glitch in this case
1 0 0
A 1 A 0 A 0
G1 G1 G1
\C \C 0 \C 1
1 1 1 1
G3 F G3 F G3 F
\A 0 \A 0 \A 1
G2 G2 G2
D 0 D 0 D 1
1 1 1

ABCD = 110 1 ABCD = 010 1 (A is still 0 ) ABCD = 010 1 (A is 1)


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Eliminating Dynamic Hazards
Very difficult!
A circuit that is static
hazard free can still
have dynamic hazards
\A 1 01
B G1 Best approach:
01
Slow G3 Design critical
\B 1 0
1 01 circuits to be two
\C G2 1 01 0 level and eliminate all
1 10 G5 F static hazards
A 0 OR, use good clocked
\B G4 10 synchronous design
10 style
V ery slow

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FSM Partitioning
Why Partition?
What if programmable logic is limited in number of inputs and
outputs that can be used in a particular device?
For PLAs, the number of product terms are limited, thus limiting the
complexity of the next state and output functions

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Partitioning the State Machine
Suppose that FSM is
partitioned so that states at
the right are in one partition
and states at the left are in
the other
How do you support
intersignaling between the
state machine partitions?
It is usually a good idea to
partition the machine so there
are as few cross links as
possible (min cut set in graph
theoretic terms)

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Partitioning the State Machine
Solution: introduce idle states SA and SB
Machine at left enters SA allowing machine at right to exit SB
When machine at right returns to SB, machine at left exits SA

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Rules for Introducing Idle States

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Example: Partitioning the Up/Down
Counter

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Example Partitioning: Traffic Light
Controller
Main Controller vs. Counter/Timer
ST triggers transfer of control
TS or TL triggers return of T00 ST
T19
control [TL]

Reset T01 T09 T10 T18


(TLC)'

HG
TLC / ST TS / ST
T02 T08 T11 T17

TS' HY FY TS'
T03 T07 T12 T16
TS / ST TL+C' / ST
FG
T04
T06 T13 T15
(TL+C')' [TS]

(a) Main controller T05 T14


(b) Counter/timer
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Partitioned FSM Block Diagram
Interface between the
two partitions are the
HR signals ST, TS, TL
HY
reset traffic light HG NOTE: Main Controller
C FR
controller
FY
and Timer use the same
FG clock and are operating
ST TS TL in a synchronous mode
timer

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Generalized Inter-FSM Signaling
Interlocked Synchronized Signaling

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Asynchronous Signaling
Also known as speed-independent signaling
Requester/client/master vs. Provider/Server/Slave

Communications
Clocked Signals Clocked
Subsys tem Subsys tem

Reques t
S1 S2
Data Flow provider
requester
client server
mas ter slav e
Acknow ledgement

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Asynchronous Signaling
First consider the common clock case (synchronous)

Req
Data
Ac k
Clk
Master asserts Request
Slave recognizes request, processes request, indicates
completion by asserting Acknowledgement
Master accepts results, removes Request
Slave see Request removed, removes Acknowledge

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Asynchronous Signaling
What if Slave cant respond in single cycle? Solution: Wait
signaling

Req
Data
Wait
Clk
Slave inhibits master by asserting wait
When slave unasserts wait, master knows request has been
processed, and can latch results

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True Asynchronous Signaling
Now remove the assumption of a single common clock
How do we make sure that receiver has seen the senders signal?
Solution: Interlocked signaling
Four cycle signaling: assert Req, process request, assert ack,
latch result, remove Req, remove Ack and start again
Sometimes called Return to Zero signaling

1 3
Req
Data
Ack 2 4

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True Asynchronous Signaling
Alternative scheme: Two-Cycle Signaling
Non-return-to-zero signaling
Transaction start by Req lo-to-hi, finishes Ack lo-to-hi
Next transaction starts by Req hi-to-lo, finishes Ack hi-to-lo
Requires EXTRA state to keep track of the current sense of
the transitionsfaster than 4 cycle case, but usually involves
more hardware

Req 1 1

Data
Ack 2 2
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True Asynchronous Timing
Self-Timed Circuits
Uses Req/Ack signaling as described
Components can be constructed with
NO internal clocks
Input Output
Determines on its own when the Combinational
request has been processed logic
Concept of the delay line simply Req Ack
slows down the pass through of the Delay
Req to the Ackusually matched to
the worst case delay path
Becoming MORE important for large
scale VLSI chips were global clock
distribution is a challenge

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Metastability and Asynchronous inputs
Clocked synchronous circuits
Inputs, state, and outputs sampled or changed in relation to a
common reference signal (called the clock)
E.g., master/slave, edge-triggered
Asynchronous circuits
Inputs, state, and outputs sampled or changed independently of a
common reference signal (glitches/hazards a major concern)
E.g., R-S latch
Asynchronous inputs to synchronous circuits
Inputs can change at any time, will not meet setup/hold times
Dangerous, synchronous inputs are greatly preferred
Cannot be avoided (e.g., reset signal, memory wait, user input)

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Synchronization Failure
Occurs when FF input changes close to clock edge
FF may enter a metastable state neither a logic 0 nor 1
May stay in this state an indefinite amount of time
Is not likely in practice but has some probability

logic 1

logic 0
logic 0 logic 1

small, but non-zero probability oscilloscope traces demonstrating


that the FF output will get stuck synchronizer failure and eventual
in an in-between state decay to steady state
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Dealing with Synchronization Failure
Probability of failure can never be reduced to 0, but
it can be reduced
(1) slow down the system clock: this gives the synchronizer
more time to decay into a steady state; synchronizer failure
becomes a big problem for very high speed systems
(2) use fastest possible logic technology in the synchronizer:
this makes for a very sharp "peak" upon which to balance
(3) cascade two synchronizers: this effectively synchronizes
twice (both would have to fail)

asynchronous D Q synchronized
D Q
input input

Clk

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synchronous system
Handling Asynchronous Inputs
Never allow asynchronous inputs to fan-out to more
than one flip-flop
Synchronize as soon as possible and then treat as
synchronous signal

Clocked Synchronizer
Synchronous
System
Async Q0 Async Q0
D Q Input D Q D Q
Input

Clock Clock

Q1 D Q Q1
D Q

Clock Clock

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Handling Asynchronous Inputs (contd)
What can go wrong?
Input changes too close to clock edge (violating setup time
constraint)

In
In is asynchronous and
fans out to D0 and D1
Q0
one FF catches the
signal, one does not
Q1
inconsistent state may
be reached!
CLK

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Signaling Summary
Glitches/Hazards
Introduce redundant logic terms to avoid them OR use synchronous
design!
FSM Partitioning
Replacing monolithic State Machine with simpler communicating
state machine
Technique of introducing idle states
Machine-to-machine Signaling
Synchronous vs. asynchronous
Four vs. Two Cycle Signaling
Asynchronous inputs and their dangers
Synchronizer failure: what it is and how to minimize its impact

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