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Concept + Research Document

MRD (market research document) --- what chip should do(10MHz)

EPRD(engineering product requirement document ) --what chip can do



(timing) (functionality)

MICRO ARCHITECTURE ------ (how chip will do)


IDEA dictated by the market translated into architecture and electrical specification

next phase is to implement of these specification into RTL CODING .

There are three levels of abstraction that may be used to represent the design into dataflow,
Behavioural, RTL (Register Transfer Level) and Structural.

Synopsys recently introduced Behavior Compiler, capable of synthesizing Behavior

level style of coding.

The next step is to check the functionality of the design by simulating the RTL code

**to check the functionality we need to provide test bench for the following RTL code**

**The main purpose of Test Bench is to provide necessary STIMULI(INPUTS) to the design**
Logic Synthesis ,Optimization
Here we are going to perform the task to reduce the RTL code in Gate Level Netlist.

Synthesis tools :
1) Synopsys : DC (DESIGN COMPILER)
2) Cadence : RTL COMPILER


These timing constraints define the relationship of each signal with respect to the clock input
for a particular block

Technology cell libraries

RTL code
Logic Synthesis ,Optimization

DC reads the RTL code of the design and using the timing constraints, synthesizes the
code to structural level, thereby producing a mapped gate level netlist
Logic Synthesis ,Optimization

Library (.lib) :

cell description
driving capacity
cell delay models
Operating Conditions (PVT)
Wire Load Models
Operating Conditions (PVT)

Process is varying due to Oxide thickness ,Vth .

Wire Load Models
Constraints file
timing constraints define the relationship of each signal with respect to the clock input

What should be defined?

1) Period and Waveform
2) Latency
Source latency
Network latency
3) Uncertainty
Clock Period & Waveform
Period: Clock cycle time

Waveform: Clock rise and fall time

Period: 10ns
Rise time: 0ns
Fall time: 5ns

1) Source Latency (OFF CHIP DELAY)

2) Network Latency (ON CHIP DELAY)
The maximum difference between the arrival of clock signals at sequential cells in one
clock domain or between domains
Out comes of Synthesis block

NETLIST : Cell to cell connectivity information

SDF (.sdf): The Standard Delay Format (SDF) file stores the timing data generated by
EDA tools.

SDC (.sdc):defines delay between two cells.

Formal Verification

It check for logical function of a design comparing it against the reference design.

1) RTL Vs Gate level NETLIST

3) Gate level NETLIST Vs Gate level NETLIST
Pre-Layout & Post-Layout

In the pre-layout mode, PrimeTime (Tool) uses the wire load models specified in the
library to estimate the net delays

In the post-layout mode, the actual extracted delays are back annotated to
PrimeTime to provide realistic delay calculation. These delays consist of the net
capacitances and interconnect RC delays
Floorplan & Placement


* Core Limited
* i/o limited

i/o limited : how much of area that we need to allocate for input and output pins

Core limited : how much of area that we need to allocate for internal blocks
Floorplan & Placement


Usage :-**For Optimization purpose**

Optimal cell placement location, not only speeds up the final routing, but also produces
superior results in terms of timing and reduced congestion

speed congestion
Clock Tree synthesis

Usage :-**reduce the total delay and skew**

using fishbone/spine structure(Virtual Clock) for the clocks in order to reduce the
total delay and skew of the clock

Spin approach : the spine approach is getting more difficult to implement due to the
increase in resistance (thus, RC delays) of the interconnect wires .

layout tool generally performs routing in two phases

1) global routing
2) detailed routing
1)GLOBAL ROUTING : After placement, the design is globally routed to determine the
quality of placement, and to provide estimated delays.

2) DETAILED ROUTING : the real timing delays of the chip are extracted .
Physical Verification

If the design passes static timing analysis, it is ready to undergo LVS (layout versus schematic)
and DRC (design rule checking)
ECO (Engineering Change Order)
ECO is performed on a small portion of the chip to prevent disturbing the placement
and routing of the rest of the chip

Modifications are accepted less than 10% in the whole chip.

If the Modifications are more than 10% in the whole chip the whole procedure is
GDSII (Geometric data stream information interchange)


Some tool vendors will call it as : Graphic Design System