INTRODUCTION

TO VLSI
 From
1945
ENIAC filled an entire room!
17,468 vacuum tubes,
70,000 resistors, and
10,000 capacitors
6,000 manual switches
and many blinking lights!
Could add 5,000 numbers in
a single second
 To
1947
Point-contact transistor
1954
first computer with no tube
800 transistors and
10,000 germanium crystal rectifiers
only 100 watts
1958
Invention of the Integrated Circuit
1958
A device having multiple electrical components and their
interconnects manufactured on a single substrate
 And To
this:
Magnified
Some packages
 Why Integrated Circuits?

• Break this question into two questions

– Why electronics
– Why use ICs to build electronics
• Why use electronics
– Electrons are easy to move/ control
• Takes much less energy and $
 Electronics
• Building electronics:
– Started with tubes, then miniature tubes
– Transistors, then miniature transistors
– Components were getting cheaper, more reliable but:
• There is a minimum cost of a component
• Total system cost was proportional to complexity
• Integrated circuits changed that
– Printed a circuit, like you print a picture,
• Create components in parallel
• Cost no longer depended on # of devices
– What happens as resolution goes up?
 Moore’s Law
• Gordon Moore: co-founder of Intel.
• Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
• Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.
Moore’s Law Plot
 Microprocessors
• Intel 80286: 16-bit microprocessor
- 52,000 transistors
• Intel 80386: 32-bit CISC(1989)
- 1M transistors (1um CMOS
technology)
• Intel 80486: 32-bit CISC (1990)
- 1.2M transistors (1um CMOS
technology)
• Intel Pentium: 64-bit CRISC (1993)
- over 3M transistors (0.8um BiCMOS
technology)
• Intel Pentium II : 64-bit CRISC (1997)
- 7.5M transistors ( 0.35um ~ 0.25um BiCMOS technology)
• Intel Pentium III : 64-bit CRISC (1999)
- 9.5M transistors ( 0.25um Net Burst micro-architecture
(2002)
• Intel Pentium IV : 64-bit) uses 1.475 Volt 2.4 GHz clock,
- 55M transistors (0.13um technology BiCMOS
technology)
 Moore’s Law Today

International Technology Roadmap of Semiconductors(ITRS)

– Projects roadmap for next 15 years
• Defined in terms of “Technology Nodes”
• 2001 => 130nm
• 2004 => 90nm
• 2013 => 32nm
 Good news, but..
• Things getting worse with each generation:
– Complexity
– Power consumption
– Power distribution
– Signal integrity
– Fabrication time
– Capital costs for equipment
– Fixed costs for masks
– Variable costs for wafers
• How do we handle these for a device with 100M gates?
 One method of Coping:
Use a Standard Processor
• Pros:
– Intel and AMD have giant design teams – leverage them
– Cost of large support infrastructure spread over huge user
community
• Cons:
– Fixed instruction set and data path
Another Method of Coping: Using a
Field Programmable Gate Array(FPGA)
• Logic pre-fabricated with reconfigurable interconnect
• Pros:
– Very fast turnaround, easier to fix mistakes
– Configurations for often used functions readily available
• Cons:
– Practical number of usable gates is about 1 million at 0.13µ
• Reaching a clock frequency of 150MHz is doing good
• Power is typically 3x that of comparable Application
Specific(ASIC)
VLSI Design Process
VLSI Design Process
The VLSI Design Process
The VLSI Design Process
Metal-oxide-semiconductor (MOS)

• pMOS
• nMOS
• CMOS
• BiCMOS
nMOS transistor structure
 Basic MOS Transistors
• Minimum line width
• Transistor cross section
• Charge inversion channel
• Source connected to substrate
• Enhancement vs Depletion mode devices
• pMOS are 2.5 time slower than nMOS due
to electron and hole mobilities
MOSFET Operation
MOSFET Operation
MOSFET Operation
MOSFET Operation
 Gate voltage and the channel
gate
current
source drain Vds < Vgs - Vt
Id

gate

current
source drain Vds = Vgs - Vt
Id

gate

source drain
Vds > Vgs - Vt
Id
nMOS transistor
pMOS transistor
 CMOS Technology
• First proposed in the 1960s. Was not seriously considered until the
severe limitations in power density and dissipation occurred in
NMOS circuits
• Now the dominant technology in IC manufacturing
• Employs both pMOS and nMOS transistors to form logic elements
• The advantage of CMOS is that its logic elements draw significant
current only during the transition from one state to another and
very little current between transitions - hence power is conserved.
• In the case of an inverter, in either logic state one of the transistors
is off. Since the transistors are in series, (~ no) current flows.
 CMOS transistor
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 BiCMOS Technology
• Deficiency of MOS technology is its limited load driving
capabilities
• Bipolar transistors have
– higher gain
– better noise characteristics
– better high frequency characteristics
• BiCMOS gates can be an efficient way of speeding up VLSI
circuits
• CMOS fabrication process can be extended for BiCMOS
• Example Applications
– CMOS - Logic
– BiCMOS - I/O and driver circuits
BiCMOS Technology
BiCMOS Technology
Making Chips
A View of Clean Room
IC Fabrication Technology
1. Select wafer
2. Oxidation
3. Photolithography
4. Masking
5. Etching
6. Polysilicon
7. Diffusion/ Ion implantation
8. Planarization
9. Metallization
10. Encapsulation
Silicon Wafer
 Fabrication Steps
• Start with blank wafer
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2
(oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate
 Oxidation

• Grow SiO2 on top of Si wafer

900 – 1200 C with H2O or O2 in oxidation
furnace

SiO2

p substrate
 Photoresist

• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate
 Lithography

• Expose photoresist through n-well mask

• Strip off exposed photoresist

Photoresist
SiO2

p substrate
 Etching

• Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate
 Strip Photoresist

• Strip off remaining photoresist

• Necessary so resist doesn’t melt in next step

SiO2

p substrate
 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with dopant gas
– Heat until dopant atoms diffuse into exposed Si
• Ion Implantation
– Blast wafer with beam of dopant ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well
 Strip Oxide

• Strip off the remaining oxide using HF

• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps

n well
p substrate
 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
 N-diffusion cont.

• Historically dopants were diffused

• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate
 N-diffusion cont.

• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate
 P-Diffusion
• Similar set of steps form p+ diffusion
regions for pMOS source and drain and
substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
 Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
Fabrication, Testing & Packaging
Final IC After Packaging
 Wafer Processing
direction of pull and rotation
crystal holder
• Czochralski process
seed
– Melt silicon at 1425 degrees C growing crystal (ingot)
– Add impurities to dope crystal
– Spin and gradually extract seed crystal
molten silicon

• Slice into wafers, 0.25mm to 1.0mm

• Polish one side, sand-blast the other
 Layering - Thermal Oxidation
SiO2 functions:

Surface passivation Diffusion barrier Field oxide MOS Gate oxide

Natural oxide: silicon will readily grow an oxide (5-10nm) if exposed to oxygen in the air!
The range for useful oxide thickness: 25nm (MOS gates) - 1500nm (field oxide)

Dry oxidation
Si + O2  SiO2 (900-1200°C)
O2
700nm oxide: 10hours (1200°C)
SiO2
Good oxide quality: gate oxide
Silicon
Wet oxidation (water vapor or steam)
Si + H2O  SiO2 + 2H2 (900-1200°C)
700nm oxide: 0.65hours (1200°C)
Poor oxide quality: field oxide
 IMPLANTATION/DIFFUSION

• Doping of silicon is done through implantation.

• Wells, source-drain regions and poly doping is done
through ion implantation and diffusion.
• Present day processes have very small thermal
budget. The source – drain junctions are very
shallow.
• Rapid thermal processing is the most preferred
technique for implant activation
• With very shallow junctions contact formation
becomes a very serious problem.
Ion Implantation
Photo Lithography
 CMOS Technology
• First proposed in the 1960s. Was not seriously considered until the
severe limitations in power density and dissipation occurred in
NMOS circuits
• Now the dominant technology in IC manufacturing
• Employs both pMOS and nMOS transistors to form logic elements
• The advantage of CMOS is that its logic elements draw significant
current only during the transition from one state to another and
very little current between transitions - hence power is conserved.
• In the case of an inverter, in either logic state one of the transistors
is off. Since the transistors are in series, (~ no) current flows.
 BiCMOS Technology
• Deficiency of MOS technology is its limited load driving
capabilities
• Bipolar transistors have
– higher gain
– better noise characteristics
– better high frequency characteristics
• BiCMOS gates can be an efficient way of speeding up VLSI
circuits
• CMOS fabrication process can be extended for BiCMOS
• Example Applications
– CMOS - Logic
– BiCMOS - I/O and driver circuits
BiCMOS Technology
BiCMOS Technology