Chapter 4

Programmable Logic Devices:

CPLDs with VHDL Design

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
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 PLD Design Flow
• Thousands of basic logic gates
• Advanced sequential functions
• Single package
• Not yet configured to perform a function

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Design Flow
• CAD to draw the schematic
• Schematic Capture to convert to binary file
• Program to alter PLD internal connections

• VHDL - Very High Speed Integrated Circuit

Hardware Description Language
– architecture body
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Design Flow
• See Figure 4-2
• Define the problem
• Develop the equations
• Enter the design
• Simulate the input/output conditions
• Program the PLD
• Test the final programmed PLD
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Figure 4-2

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Design Flow
• Implementing X=AB + B + C
– Using 7400 series ICs
– Using a PLD

• Altera Corporation tools

– MAX+PLUS II (entry-intermediate level)
– Quartus II (more advanced)
– UP-1 or UP-2
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Architecture
• SPLDs
– most basic
– least expensive
– configurable logic gates
– programmable interconnection points
– may have memory flip-flops
– typically 16 inputs and 8 outputs
– product terms from AND gates

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Architecture
• PALs
– programmable array logic
– gives Sum-of-Products form
– uses OR gate
• PLAs
– programmable logic array
– uses programmable OR gates
• Flip-flop memory section
• Data steering circuitry
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Architecture
• PAL16L8 is a typical PAL device
– 16 indicates 16 inputs
– 8 indicates 8 outputs
– L means outputs are active LOW
• Refer to the data sheet for a logic diagram

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Architecture
• CPLDs
– complex programmable logic devices
– combine several PAL-type SPLDs into single
package
– non-volatile
– repeatedly programmed

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 PLD Architecture
• FPGAs
– field-programmable gate arrays
– uses a look-up-table
– more dense than CPLD
– memory is volatile
– see figure 4-11

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Figure 4-11

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Using PLDs to Solve Basic Logic
Designs
• Block editor
– connect pre-defined logic symbols
• VHDL editor
– define the logic
• Compiler
– language and symbol translation program
• Waveform Simulator
– to check the logic operation
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Using PLDs to Solve Basic Logic
Designs
• Using Quartus II CPLD software to
implement a 2 input AND gate
– See figure 4-13(a) for a screenshot of a block
editor version
– See figure 4-13(b) for a screenshot of a VHDL
text version
• library
• declaration
• entity declaration
• architecture body
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Using PLDs to Solve Basic Logic
Designs
• Using Quartus II CPLD software to
implement a 2 input AND gate
– Figure 4-13(c) is a screenshot of the waveform
editor after simulation

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
Figure 4-13(a)

Figure 4-13(b)

Figure 4-13(c)
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Tutorial for Using Altera’s
Quartus II Design Software
• Build a solution to X=AB + CD
– create a block design file
– assign the file a name
– specify a project name
– draw logic circuits
– add input and output pins
– connect the symbols
– assign a device to implement the design
– save and compile to check for errors
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Tutorial for Using Altera’s
Quartus II Design Software
• Test and simulate the solution to
X=AB + CD
– create a new vector waveform file
– assign the same name as the design file
– create node names for inputs and outputs
– develop 4 input waveforms to cover all 16
possible inputs
– compile and simulate to verify that output
satisfies equation
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Tutorial for Using Altera’s
Quartus II Design Software
• Programming the PLD using the Altera
UP-2 or the RSR PLDT-2 programmer
board
– downloads logic design to actual PLD
– the EPM7128S CPLD
– configuring and connecting UP-2 programmer
board
– see figure 4-39

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Figure 4-39

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Tutorial for Using Altera’s
Quartus II Design Software
• Programming the PLD using the Altera
UP-2 or the RSR PLDT-2 programmer
board
– configuring and connecting PLDT-2
programmer board
– see figure 4-40

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Figure 4-40

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Tutorial for Using Altera’s
Quartus II Design Software
• Programming the PLD using the Altera
UP-1 or the RSR PLDT-2 programmer
board
– connect switches and LED to CPLD pins
– assign pin numbers in the boolean1.bdf file
– connect wires to the input stimulus switches
and output LED
– download (program) the CPLD
– test the downloaded design
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 CPLD Applications
• Follow the step by step process from section
4-4 to implement the following:
– X=AB + AB
– X=ABC
– X=ABC + ABC

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Summary
• Programmable Logic Devices can be used
to replace 7400-series and 4000-series ICs.
They contain the equivalent of thousands of
logic gates. Computer-Aided Design
(CAD) tools are used to configure them to
implement the desired logic.

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Summary
• The two most common methods of PLD
design entry are graphic entry and VHDL
entry. To use graphic entry the designer
uses CAD tools to draw the logic that needs
to be implemented. To use VHDL entry the
designer uses a text editor to write program
descriptions defining the logic to be
implemented
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Summary
• PLD design software usually includes a logic
simulator. This feature allows the user to
simulate levels to be input to the PLD and
shows the output simulation to those input
conditions.
• Most PLDs are erasable and re-programmable.
This allows the user to test many versions of
their logic design without ever changing ICs.
Copyright ©2006 by Pearson Education, Inc.
William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Summary
• Basically there are three types of PLDs:
SPLDs, CPLDs and FPGAs. SPLDs consist
of several multi-input AND gates feeding
the inputs to OR gates and memory flip-
flops. The CPLD consists of several
interconnected SPLDs. The FPGA is the
most dense form of PLD. It solves its logic
using a look-up table to determine the
desired output.
William Kleitz
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version