ECE-E434 Digital Electronics

Lecture # 9&10: Pseudo-NMOS Inverter

& Pass-logic Digital Circuits

Instructor: Pouya Dianat

Oct 26 & 27 2017
 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Digital IC Technologies

Advantages of CMOS Logic ICs:

• Less power dissipation  More packing density on the chip.
• High input impedance  Use of temporary charge storage  Memory and Logic Operations
• Very small feature size  at 22nm manufacturing node

Advantages of Bipolar Logic ICs:

• Very high speed of operation
 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Pseudo-NMOS Inverter
• Advantage over CMOS: One MOS transistor per input
• If there are more than one input for the inverter:
• Less area occupied on the chip
• Time-delay associated with numerous inputs is less
ACTIVE LOAD

Problems: • A constant current source 

• Small Noise Margin Excellent load
• Large Static Power Dissipation
• Body effect limits its
• Small Logic Voltage Swip performance

Figure 15.10 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The
depletion-load NMOS inverter.
 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Reminder: The body effect

The body effect can be seen as a change/increase in threshold voltage

 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Static Operation of a Pseudo-NMOS

a.k.a Ratioed Inverter

Design Factors: >

 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Static Operation of a Pseudo-NMOS

 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Static Operation of a Pseudo-NMOS

 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Noise Margin and Dynamic Operations

of pseudo-NMOS Inverter
All parameters depend on ratio r, hence the name
“ratioed inverter”

Question: Knowing typically 4<r<10, how do tPLH and tPHL compare? Is the operation
symmetric? Suggest a suitable application for the ratioed inverter.
 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Let’s Review: The effect of r

1. Select r: typically between 4 and 10. Compromise between: Speed, NM, Silicon area
2. Select W/L: Compromise between speed and Power (Istat)
• Typically select: 50mA<Istat<100mA

Viable cases for pseudo-NMOS: When output is mostly high  Low static power
 ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15

Gate Circuits based on pseudo-NMOS