8051

Micro-Controller 8051
Overview
주식회사 H.I 시스템

MCS-51 Family Overview
80C51 Family Products
 Pin Compatible
Internal Memory
DEVICE Timer Interrupt
Program Memory Data Memory
8031AH NONE 128x8 RAM 2 x 16 -Bit 5

8051AH 4Kx8 ROM 128x8 RAM 2 x 16 –Bit 5
8051AHP 4Kx8 ROM 128x8 RAM 2 x 16 –Bit 5
8751H 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5
8751H-8 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5
8751BH 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5
8032AH NONE 256x8 RAM 3 x 16 -Bit 6
8052AH 8Kx8 ROM 256x8 RAM 3 x 16 –Bit 6
8752BH 8Kx8 EPROM 256x8 RAM 3 x 16 –Bit 6
MicroProcessor Part II 2
Architectural Structure of the 8051 Family
FREQUENCY REFERENCE COUNTERS
OSCILLATOR ROM RAM TWO 16-BIT

& / EPROM TIMER/EVENT
TIMMING COUNTERS
CPU
64K BYTE BUS • PROGRAMMABLE

PROGRAMM-
EXPANSION SERIAL PORT
ABLE I/O
CONTROL • FULL DUPLEX UART
• SYNCHRONOUS SHIFTER
Int INTERRUPTS
Ext INTERRUPTS CONTROL PARALLEL PORTS

ADDRESS DATA BUS SERIAL IN / SERIAL OUT
I/O PINS
Internal Block Description
Part Contents
Interrupt Control Ext / Internal Interrupts, Masking, Priority
Central Processing Unit Arithmetic / Logical Operation , Control
Internal Program Memory
ROM
4KB or 8KB : ROM ( = 805X ), EPROM ( = 875X )
RAM Internal Data Memory
4 x 8bit I/O port 4Byte I/O port ( P0 ~ P3 )
Serial Port Rcv/Snd 1 bit data.
Controller - Periodic Operation
Timer / Counter Event Counting, Check PulseWidth
Send periodic Interrupt to CPU
PSEN
External Program Control Signal
(Program Strobe Enable )
ALE (Address Latch Enable) Separate Address & Data
0V : Read PRG from External Memory
EA (External Access)
5V : Read PRG from Internal Memory
RST ( ReSeT) Reset port
Main Features of 8051
Part Function
Data Bit-Width 8 Bit
Arithmetic Operation.
Computation
Logical Operation
Data – External Memory 64KB , Internal Memory 128B
Memory Size
PGM – External Memory 64KB , Internal Memory 4KB
Parallel I/O port – 32 ( 4 x 8 Bit )
Communication
Serial I/O port – Full Duplex UART
2 x 16-Bit Timer , Clock Generator
Etc
5 Interrupts
UART : Universal Asynchronous Receiver/Transmitter
External Pin Description
P0.7 AD7
P0.6 AD6
P0.5 AD5
P0.4 AD4 Address/Data Bus
P0.3 AD3
P0.2 AD2
Bidirection I/O Port
P0.1 AD1
P0.0 AD0
/PSEN
P1.7
ALE P1.6
P1.5
/EA P1.4
P1.3 Bidirection I/O Port
/RST P1.2
P1.1
P1.0
RD P3.7 P2.7 A15
WR P3.6 P2.6 A14
T1 P3.5 P2.5 A13
Bidirection T0 P3.4 P2.4
INT1 P3.3 P2.3
A12 Address Bus
I/O Port A11
INT0 P3.2 P2.2 A10 Bidirection I/O Port
TXD P3.1 P2.1 A9
RXD P3.0 P2.0 A8
Executing From External Program Memory
Timing
CLK
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4
ALE
/PSEN
PORT2
PORT0
LATCH
Bus Cycle
Structure
DATA(AD7~AD0)
P1 P0 EPROM
8 /EA A7~A0
0 LATCH
5 Lower Addr.
1 ALE Addr
Upper Addr. (A15~A8)
P3 P2
/OE
/PSEN
Example 87h
EPROM
Read P1 P0
Address 0421h 8 /EA
0 LATCH
(87h) 5
1 ALE Addr
P3 P2 /OE
/PSEN
Upper Address : 04h

Lower Address : 21h
EA : High : Internal Data Memory P0 : Address / Data I/O Port

EA : Low : External Data Memory P2 : Address Bus
Executing From External Data Memory
Structure
P1 P0
RAM
8
0 LATCH
5
1 ALE Addr 216
( 0~64KB)
= 64KB
RD P3
P2
WR
/CE
DECODING WR /OE
Timing - Read
CLK
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4
ALE
PSEN
／ＲＤ
PORT2
PORT0
LATCH
Bus Cycle
Timing - Write
CLK
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4
ALE
PSEN
／WR
PORT2
PORT0
LATCH
Bus Cycle
Instruction Decoder
ACCUMULATOR TEMP REG FLAG INSTRUCTION

REGISTER
AND DECODER
ACCUMULA-
ARITHMETIC INT0
TOR LATCH
BRANCH LOGIC
LOGIC INT1
CONDITION
UNIT CARRY
ACC
TIMER
1. Store the OP Code ….
2. Decoding …
DECIMAL
3. Output Control Signal ADJUST
Arithmetic Logic Unit

REGISTER
AND DECODER
ACCUMULA-
ARITHMETIC INT0
TOR LATCH
BRANCH LOGIC
LOGIC INT1
CONDITION
UNIT CARRY
ACC
Input : 1 or 2 x 8bit data TIMER
Output : 8bit result data ….
1. +, - (carry) …
DECIMAL
2. Increment, Decrement
ADJUST
3. Bit Complement
4. Rotate Left/Right
5. Nibble Exchange
6. *, /
Accumulator

REGISTER
AND DECODER
ACCUMULA-
ARITHMETIC INT0
TOR LATCH
BRANCH LOGIC
LOGIC INT1
CONDITION
UNIT CARRY
ACC.
TIMER
1. Store Input Data …
2. Store Result Data ....
DECIMAL
3. Transfer data to ADJUST
Memory and I/O
CPU Timing (I)
Machine Cycle consists of six states ( 12 oscillator periods)
OSC
(xtal1)
ALE
STATE S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1-BYTE, 1-CYCLE Instruction (INC a ) READ NEXT OPCODE AGAIN
READ OPCODE READ NEXT OPCODE ( DISCARD)
2-BYTE, 1-CYCLE Instruction (ADD a , #data ) READ NEXT OPCODE
READ OPCODE READ 2nd BYTE
CPU Timing (II)
OSC
(xtal1)
ALE
READ
NEXT
OPCODE
AGAIN
1-BYTE, 2-CYCLE Instruction (INC DPTR )
READ OPCODE
READ NEXT OPCODE ( DISCARD )
CPU Timing (III)
OSC
(xtal1)
ALE
1-BYTE, 2-CYCLE Instruction (MOVX)
READ OPCODE NO FETCH NO FETCH

READ NEXT
OPCODE ( DISCARD )
ACCESS EXTERNAL MEMORY
Memory Organization
Logical Separation of Program and Data Memory

PROGRAM MEMORY DATA MEMORY
(READ ONLY) (READ/WRITE ONLY)
FFFF FFFF
216 Ext
Ext
0FFF
FF
Int Int
4KB /EA=0 /EA=1
=4096B Ext Int
Int
0000 00
/ PSEN / RD / WR
Program Memory
 After reset, the CPU begins execution from location 0000h
 The interrupt causes the CPU to jump to that location, where it

commences execution of the service routine
Ex) External Interrupt = 0003h
 The lowest 4K bytes of program memory can be either in the On-chip

ROM or in an External ROM ( /EA (=External Access ))
 The read Strobe to external ROM, /PSEN, is used for all external
program fetches. /PSEN is not activate for internal program fetches.
Program Memory
Internal Program Memory : Lower 4KB region of the program memory

0FFF
Longer service routines can be jump

PROGRAM
instruction
LOCATIONS
002B
If an interrupt service routine is short
0023
enough ( as is often the case in control
001B applications), it can reside entirely
INTERRUPT within that the 8-byte interval.
LOCATIONS 0013
8 BYTE
000B
0003
RESET 0000
Data Memory
 Internal Data Memory space is shown divided into three blocks, which are generally
refereed to as the lower 128, the Upper 128, and SFR space
 Internal Data Memory Address are always 1 byte wide ( 256Byte )
FF
Accessible by PORTS
direct Addressing STATUS BIT
UPPER 128 CONTROL BIT
Special Function Registers TIMER
REGISTERS
80 STACK POINT
7F ACCUMULATOR
Accessible by indirect (ETC..)
LOWER 128
Addressing only
00
Accessible by direct
and indirect addressing
The Lower 128 Byte of internal RAM
The Lower 128 Byte of internal RAM
3F ~ 7F STACK
20 ~ 2F BIT-ADDRESSABLE SPACE
11 18 ~ 1F
BANK
SELECT 10 10 ~ 17
4 BANKS OF REGISTER (R0~R7)
BIT IN 01 08 ~ 0F
PSW
00 00 ~ 07
4 Banks Of Register
4 X 8 REGISTER BANK
R7
R6
R5
R4
R3
R2
R1
R0 4th REG. BANK
3rd REG. BANK
2nd REG. BANK

R7
R6
R5
R4
R3
R2
R1 1st REG. BANK
R0
Bit-Addressable Register
7F 7E 7D 7C 7B 7A 79 78 2Fh Boolean Instruction ( Bit Operation )

77 76 75 74 73 72 71 70 2Eh
AND, OR, CLEAR, SET
COMPLEMENT, MOVE BIT …..
Ex) ANL CY, Bit Address

CY
AND CY
Bit Address
ANL CY, 27h.3

Before : CY 1
(27h) 0 0 1 0 1 1 1 0
After : CY 1
0F 0E 0D 0C 0B 0A 09 08 21h
07 06 05 04 03 02 01 00 20h
Special Function Register (SFR) - (I)
1. Software Control/Operation ( Acc, B, DPTR, PSW, SP )

2. Internal Unit Control
Internal Bit/Byte
Register Mnemonic
Address Access
Port 0 Latch P0 80 Bit
Stack Point SP 81 Byte
Data point ( Word ) DPTR 82 ~ 83 Word
Data point Low Byte DPL 82 Byte
Data point High Byte DPH 83 Byte
Power Control PCON 87 Byte
Timer/Counter Control TCON 88 Bit
Timer/Counter Mode Control TMOD 89 Byte
Timer/Counter 0 Low Byte TL0 8A Byte
Timer/Counter 1 Low Byte TL1 8B Byte
Timer/Counter 0 High Byte TH0 8C Byte
Timer/Counter 0 High Byte TH1 8D Byte
Special Function Register (SFR) - (II)
Internal Bit/Byte
Register Mnemonic
Address Access
Port 1 Latch P1 90 Bit
Serial Port Control SCON 98 Bit
Serial Data Port SBUF 99 Byte
Port 2 Latch P2 A0 Bit
Interrupt Enable IE A8 Bit
Port 3 Latch P3 B0 Bit
Interrupt Priority Control IP B8 Bit
Program Stats Word PSW D0 Bit
Accumulator Acc or A E0 Bit
B Regster B F0 Bit
Special Function Register (SFR) - (III) - Software Control/Operation
 Acc : 8 Bit Accumulator ( Arith./Logical Operation)
 B : General Purpose Register : X , /
 DPTR : 16Bit Register , 8-bit accessable.

( using address pointer in the transmit External Data transfer )
 PSW : 8 Bit -Register,

( carry, Overflow, Parity Flag, Selection of the Register Bank )
 SP : Stack Point , 8-Bit Register
Special Function Register (SFR) - (III) - Internal Unit Control
 Timer/Count
: TH1, TL1, TH0, TL0, TMOD, TCON
 Serial Port
: SBUF, SCON, PCON
 Interrupt control
: IE, IP
 I/O Port
: P0, P1, P2, P3
Chap2 . The Instruction of 8051 Family
Instruction Set
5 Groups - 51 Instructions
1. Data Transfers Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Boolean Instructions
5. Jump Instructions
The Concepts of OPCODE & OPERAND
Instruction Code
1 Byte Instr.
OP Code + Operand
(Specification of the Operation) (Specification of the Address)
The length of an Instruction depends on

1. The number of operands it involves
2. The Way it specifies each operands
Some Inst. Formats of the Intel 8085
Single-byte zero address Instruction

Opcode
Operand field 1
Single-byte one address Instruction Operand field 2
Single-byte two address Instruction
Two-byte one address Instruction
Three-byte one address Instruction
 Every general-purpose computer has its own unique instruction.

 The Instruction Code is a group of bits that tell the computer to perform
a specific operation.
 Operation Code
: It define such operations as add, subtract, multiply, shift, and
complement.
Total number of operations obtained determines the set of machine
operations.
Opcode must consist of at least n bits for a given 2n (or less) distinct
operations.
 Instruction (=Macro-Instruction) = The Sequences of Micro-Instruction
1. Data Transfer Instructions
 1. The Immediate Addressing Mode

 2. The Direct Addressing Mode
 3. The Register Addressing Mode
 4. The Register-Specific Addressing Mode
5. The Register Indirect Addressing Mode
6. The Register Indexed Addressing Mode
1.Data Transfer Instruction - The Immediate Addressing Mode
 The Immediate Addressing Mode

: Immediate addressing, or perhaps more explicitly, immediate constant
addressing, refers to the source being a constant embedded into code.
Mov a , #1 ; { 74 01h } = { Opcode + Operand }
Include Data
Register(Acc, SFR), Memory
Org 8000h ; set the origin
mov a, #0h ; put 0 into the accumulator
mov a, #11h ; put 11h into the accumulator
mov a, #27 ; put 27(Dec) = 1bh into the accumulator
• Start Addressing : 8000h of external RAM

• The sequence of Accumulator : ??h > 00h > 11h > 1bh
1. Data Transfer Instruction - The Immediate Addressing Mode
Ex )
MOV A , #33h MOV DPTR , #1234h
PROGRAM DPTR
ACC PROGRAM
MEMORY MEMORY DPH DPL
33h 12h 34h
74 OP CODE 90 OP CODE
33 IMMEDIATE DATA 12 IMMEDIATE DATA
34
1. Data Transfer Instruction - The Immediate Addressing Mode
Ex ) Org 8000h ; set the origin

mov psw, #0 ; select register bank 0
mov r0, #0 ; put 0 into register0
mov psw, #8 ; select register bank 1

mov 70h, #0 ; put 0 into internal register 70
mov 71h, #1 ; put 1 into internal register 71

mov DPTR, #1234h ; place 12h into DPH and 34h DPL
1. Data Transfer Instruction - The Direct Addressing Mode
 The Direct Addressing Mode

: The Direct addressing mode refers to specifying an internal data register
or an SFR by its address.

mov a, 70h ; copy contents of internal register 70h to a
mov a, #0 ; clear the accumulator
mov 90h, a ; copy the accumulator contents to SFR 90h
MOV ……. , ……..
Internal Data Memory  Acc, Reg ..

Internal Data Memory  Internal Data Memory
Ex )
mov A , 33h mov 30h , R7
DATA DATA
MEMORY ACC R7 MEMORY
D1 DE
33h D1 DE 30h
DATA
DATA
< Instr. Code >

mov A , #33h : 74 33
mov A , 33h : E5 E0
Ex )
mov 30h , 35h mov 06h , 00h
PROGRAM DATA PROGRAM DATA

MEMORY MEMORY MEMORY MEMORY
DATA
85 30h D1 85 00h DE
30 06
35 00
35h D1 06h DE
DATA
Ex )
Port 4 equ 0E8h ; port 4
Port 1 equ 090h ; port 1

mov a, Port4 ; copy the contents of port 4 (= E8h)
mov Port1, a ; copy the acc. contents to contents of
port 1
ljmp 8000h ; repeat
1. Data Transfer Instruction - The Register Addressing Mode
 The Register Addressing Mode

: The Register addressing mode refers to either the source or the
destination being one of the eight registers of the currently selected
register bank.
MOV PSW, #00010000B ; BANK SELECT (BANK1)

MOV A, #30h ; Immediate Addressing Mode
MOV R1, A ; R1 = 30h
MOV R3, #20h 1010 1011 0010 0000
MOV R0, R1 ; REG  REG (X)
Cf ) Program Status Word (PSW)
 The PSW contains several status bit that reflect the current
state of the CPU.
CY AC F0 RS1 RS0 OV P
PSW7 PSW0
CARRY FLAG RECEIVES CARRY OUT PARITY OF ACCUMULATOR SET
FROM BIT 1 OF ALU OPERANDS BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0
PSW6
AUXILARY CARRY FLAG RECEIVES CARRY OUT PSW1
FROM BIT 1 OF ADDITION OPERANDS USER DEFINABLE FLAG
PSW5 PSW2
GENERAL PURPOSE STSTUS FLAG OVERFLOW FLAG SET
BY ARITHMETIC OPERATIONS
PSW4
REGISTER BANK SELECT BIT 1 PSW3
REGISTER BANK SELECT BIT 0
1. Data Transfer Instruction - The Register-Specific Addressing Mode
 The Register-Specific Addressing Mode

: Some instructions are specific to the registers used.
inc a ; increase contents of accumulator

; 04h
inc DPTR ; increase contents of DPTR
; A3h
org 8000h ; set the origin

mov a, #1 ; move the contents 1 into the accumulator
mov 0E0h,#1 ; move the contents 1 into SFR E0h
ljmp 0 ; return to the monitor
mov a, #1 ; move the contents 1 into the accumulator
PROGRAM
MEMORY
“take the following byte and place in the accumulator”

74 = the accumulator being the destination is implicitly coded
01 in the instruction
mov 0E0h, #1 ; move the contents 1 into SFR E0h
PROGRAM
MEMORY
the following 2 bytes

75 first is the address of register
E0
put the second byte to E0h ( = SFR )
01
01 E0h
= SFR
1. Data Transfer Instruction - The Register Indirect Addressing Mode
 The Register Indirect Addressing Mode

: The address of the source or destination is not given explicitly.
Instead, the contents of a register is used as the target address.
org 8000h ; set the origin

mov PSW, #0 ; select register 0
mov R0, #78h ; move 78h into register 0
mov @R0, #1 ; set the register whose address is specified in
; the R0 register to the constant 1
ljmp 0 ; return to the monitor
1. Data Transfer Instruction - The Register Indirect Addressing Mode
mov R0, # 40h mov R1, # 50h

mov A, @R0 mov @R1, #ADh
Acc
DATA DATA
MEMORY 35 MEMORY
40h 35 50h AD
1.Data Transfer Instruction - The Register Indirect Addressing Mode
mov @R0, 40h
DATA
MEMORY
40h 55
R1 55
Addressing Mode - The Source & Destination of MOV Instruction
INTERNAL
DATA 7Fh FFh mov 77h, DPL
MEMORY SFR
mov b, a
00h 80h mov a, 88h

mov 33h, R7
R7 REGISTERs
R6
Acc R5
R4
R3
mov a, 77h R2
R1
mov 10h, 77h mov a, R3 R0
Addressing Mode - The Source & Destination of MOV Instruction
mov 10h, 77h mov @R1, #33h
mov 33h, R7
Direct mov 3Fh, #33h
Addressing
Register Indirect
R0 ~ R1 Addressing
Immediate
Acc Data
mov a, #33h
1. Data Transfer Instruction - The Register Indexed Addressing Mode
 The Register Indexed Addressing Mode

In this mode, the source or destination address is obtained by adding the value
held in the accumulator to the base address. The base address may either be
the data pointer DPTR, or the program counter PC.
Register Indirect Addressing

@ Base Register + Index Register
DPTR, PC Acc
mov a , @a + DPTR
mov a , @a + PC
mov a , @a + DPTR mov a , #1 PROGRAM

MEMORY
mov DPTR, #1000h
mov a, @a + DPTR
PROGRAM
Acc MEMORY Acc
1000h 30
3A 1 31
DPTR + 1EADh 3F DPTR + 32
1E73 1000 33
Acc Acc 34
3F 31
Org 2000h
PROGRAM mov a , #10h
MEMORY
movc a, @a + PC
2000h 74
mov a , #10h Acc
2001h 10 10h
2002h 83 movc a , @a+PC
+
2003h Current PC
PC
2003h 55h
2013h 55
1. Data Transfer Instruction - The Stack Oriented Data Transfer
 The Stack Oriented Data Transfer

: Another form of register indirect addressing is implemented with push
and pop instructions. These instructions use the SFR stack pointer (SP)

mov SP , #4Fh ; initialize stack point
mov a, #45h ; put 45h in the accumulator
push acc ; push the accumulator
mov b, #0 ; clear the B register
pop b ; pop top of stack into the B register
push acc ; Note that the operand acc is the symbol define to be 0E0h.
push a ; ( X ) : it uses the register-specific addressing mode.
1. Data Transfer Instruction - The Bit Oriented Data Transfer
 The Stack Oriented Data Transfer

 Micro-Controller often manipulates single-bit data signals
 ( Ex ) pushbutton , a motor driver, Bit-Addressable Access)

mov C , P1.0 ; move the button state into carry flag
mov P1.1, C ; move the carry flag to the LED
ljump 8000h ; repeat

Vcc
..
..
Architecture P1.2
P1.1
P1.0
..
..
2. Exchange Instruction
 Exchange Instruction
: Exchange Instructions perform powerful two-way data transfers without
the need for a temporary storage byte.
Two Exchange operations :
1. Byte-wise XCH
2. Nibble-wise XCHD (exchange digit)
XCH a , <Source> XCHD a , Ri

R0~R7
@R0,@R1 @R0,@R1
Direct Address Mode
Acc Source Acc Source
Byte Nibble
2. Exchange Instruction
XCH a , R5 XCH a , @R1
a R5 a @R1
Before 15 78 Before 12 34
After 78 15 After 34 12
XCH a , 30h
XCHD a , @R0
a (30h) a @R1
Before A5 37 Before 56 78
After 37 A5 After 58 76
2. Data Processing Instruction - Arithmetic Instructions
 INC/DEC Instruction
: Register-specific, Register, Direct, Register Indirect Addressing
: Loop Counters, Pointers
Mnemonic :
INC Source Operand : Source Data = Source Data + 1
DEC Source Operand : Source Data = Source Data - 1
INC a
Acc CY AC OV P
Before FF -- -- -- X
After 00 -- -- -- 0
DEC a
Acc CY AC OV P
Before 00 -- -- -- X
After FF -- -- -- 1
INC 30h INC DPTR DEC DPTR DEC DPL

DEC DPH
 ADD/SUB Instructions
1. ADD a, Source Operand Acc Acc Src Data
2. ADDC a, Source Operand Acc Acc Src Data CY
3. SUBB a, Source Operand Acc Acc Src Data CY
Multi-Byte Adding
Acc, R0~R7
@R0, XXh
#XXh
C 16Bit C 8Bit C 8Bit
Ex ) ADD a, #32h
Acc CY AC OV P PSW
Before 76 -- -- -- --
After A8 -- -- 1 0
Sign Bit
0111 0110 (76h) (+)
Over Flow Flag + 0011 0010 (32h) (+)
(+) + (+ )
----------------------------
-128 ~ + 127
1010 1000 (A8h)
Result ( - ) ?
Ex ) ADD a, @R1 @R1 = 62h
Acc CY AC OV P
Before 86 -- -- -- --
After E8 -- -- 0 0
Sign Bit
1000 0110 (86h) (-)
(-) + (+) = (-) + 0110 0010 (62h) (+)
O.K.
----------------------------
1110 1000 (E8h)
Result ( - )
Ex ) ADDC a, 50h Addr 50h = 4Eh
Acc CY AC OV P
Before 55 1 -- -- --
Sign Bit
After A3 0 0 1 0
0101 0101 (55h) (+)

+ 0100 1110 (4Eh) (+)
Over Flow Flag
-128 ~ + 127 + 1 (+)
----------------------------
1010 0011 (A3h)
For Multi-Byte Add Result ( - )
Ex ) ADDC a, R5 R5 = 58h
Acc CY AC OV P
Before E9 0 -- -- --
Sign Bit
After 41 1 1 0 0
1110 1001 (E9h) (-)

+ 0101 1000 (58h) (+)
+ 0 (..)
Over Flow Flag ----------------------------
-128 ~ + 127 1 0100 0001 (41h)
Result (+ )
Ex ) SUBB a, @R0 R0 = 37h Barrow
Acc CY AC OV P 0110 0 11110

Before 53 1 -- -- --
After 1B 0 1 0 0
0101 0011 (53h) (+)

- 0011 0111 (37h) (+)
- 1 (+)
(+) - (+) = (+) ----------------------------
O.K. 0001 1011 (1Bh)
For Multi-Byte Sub Result (+ )
 Multiplication Instructions
MUL AB B Acc B Acc

MSB LSB
OV Flag = Set ( if Acc > 255 )
mov a , #31h ; move the 31 into Accumulator

mov b , #10h ; move the 10 into B register
mul ab ; Acc X B
B Acc B Acc
03 10 10 31
MSB LSB
 Division Instructions
B Result(portion)
DIV AB Acc / B
Acc Remainder
OV Flag = Set ( if B Reg = 0 )
mov a , #118; move the 31 into Accumulator

mov b , #5 ; move the 10 into B register
div ab ; B / Acc
B Acc Acc B
3 17 76 / 5
2. Data Processing Instruction - Logical Instructions
 Byte-wise Logical Operations

Inst. Destination Source
ANL R0 ~ R7
ORL Acc , @R0, @R1 ..
XRL Direct Addressing
# Data
ANL
ORL Acc
Direct Addressing , # Data
XRL
CPL
CLR Acc
SWAP
CLR A CLR A CPL A CPL A

(CLear Acc ) (ComPlement Acc)
Before 10110101 b (B5h) Before 10110101 b (5Bh)
After 00000000 b (00h) After 01001010 b (4Ah)
ANL Dest, Src ORL Dest, Src
ANL 37h , #11110000 b ORL a , R4
Before (37h) # 01110111 b Before (Acc) # 01110111 b

(R4) #11110000 b
#11110000 b
After (37h) #01110000 b After (Acc) #11110111 b
XRL Dest, Src
XRL a , @R0 XRL P1 , #51h
Before (Acc) # 10010001 b Before (P1) # 01010011 b

(@R0) # 11100011 b # 01010001 b
After (Acc) # 01110010 b After (P1) # 00000010 b
RL Acc RR Acc
(Rotate Acc Left ) (Rotate Acc Right )
MOV a , # 37h MOV a , # 37h

RL a RR a
RL a RR a
RL a RR a
RL a RR a
a = # 73h a = # 73h
RLC Acc RRC Acc
(Rotate Acc & Carry Left ) (Rotate Acc & Carry Right )
CY CY
CY Acc CY Acc
Before 1 00011001 Before 1 10011000
After 0 00110011 After 0 11001100
SWAP Acc
(SWAP Acc)
Acc
Before 11000011
After 00111100
2. Data Processing Instruction - Boolean Instructions
• Bit Operation = Carry Flag ( CY ) = Bit Accumulator

cf) Byte Operation = Accumulator
Bit Operation CY Bit Addressable Range
ANL C, Bit Address Ex) ANL C, 20h.5

ORL C, Bit Address Ex) ORL C, A.7
CPL C Ex) CPL C
Bit Address Ex) CPL 23h.7
SET C Ex) SET C
Bit Address Ex) SET 40h
CLR C Ex) CLR C
Bit Address Ex) CLR 28h.0
2. Data Processing Instruction - Boolean Instructions
Bit Transfer CY Direct Address
MOV C, Bit Address Ex) MOV C, 20h.5

Before CY 0
(20h) 10101100
After CY 1
MOV Bit Address, C Ex) MOV 26h.0, C

Before CY 1
(26h.0) 11000010
After (26h.0) 11000011
2. Data Processing Instruction
Program Counter
 On Power-On-Reset : PC is RESET ( 0000h )

 1 Byte Instruction Fetch : PC = Current PC + 1
 The address pointer of next instruction
Program Flow Control Instructions
1. Branch Instructions
2. Subroutine Calls
3. Interrupts
2. Data Processing Instruction - Unconditional Jump Instructions
1. Unconditional Jump Instructions
1. SJMP < Realtive Address > : Short Jump

2. AJMP < Address 11 > : Absolute Jump
3. LJMP < Address 16 > : Long Jump
4. JMP @A+DPTR : Long Jump ( Indexed Addressing )
1. SJMP < Realtive Address > : Short Jump

Signed 8 Bit (-128 ~ +127)
PROGRAM
MEMORY
SJMP 06h
051Eh 80
051Fh 06
0520h Current PC
??
0520h +
0526h 0526h
Org 0300h
SJMP BOT
User : JMP
…
CAA : MOVE A, R1
RANGE
-128 ~ 127 … Compiler
( If Range (-128 ~ 127 ))
…
BOT : INC A SJMP

….
….
2. AJMP < Address 11 > : Absolute Jump
AJMP 01D2h
083Fh 21
0840h 01D2 = 0000 0001 1101 0010
D2
0841h
?? 0841 = 0000 1000 0100 0001
Current PC
09D2h
09D2 <= 0000 1 001 1101 0010
11 Bit Address => Jump range ( ~ 2KB )

Saving 1 Byte ( cf. LJMP : 2 Byte )
3. LJMP < Address 16 > : Long Jump
LJMP 0A3Eh
0056h 02 3BYTE
0057h 0A
0058h
PC : 0A3E
3E
0A3Eh
0A3Fh
Org 0300h
LJMP BOT
User : JMP
…
CAA : MOVE A, R1
RANGE
~ xxx … Compiler
( If Range :
…
over -128 ~ 127 )
BOT : INC A
…. LJMP
….
4. JMP @A+DPTR : Long Jump ( Indexed Addressing )
JMP @A+DPTR
03A7 73 Acc DPTR
0C 0410
PC
041C
2. Data Processing Instruction - Conditional Jump Instructions
2. Conditional Jump Instructions
1. JZ < Relative Address > :

2. JNZ < Relative Address > :
3. JC < Relative Address > :
4. JNC < Relative Address > :
5. JB < Bit > , < Relative Address > :
6. JNB < Bit > , < Relative Address > :
7. JBC < Bit > , < Relative Address > :
8. CJNE A , Direct , < Relative Address > :
9. CJNE A, #Data , < Relative Address > :
10. CJNE Rn , #Data , < Relative Address > :
11. CJNE @Ri , #Data , < Relative Address > :
12. DJNZ Rn , < Relative Address > :
13. DJNZ Direct , < Relative Address > :
2. Data Processing Instruction - Call & Return Instructions
3. Call & Return Instructions
1. ACLL < Address 11 > : ( Range : 2KByte )

2. LCALL < Address 16 > : ( Range : 64KByte )
3. RET : Pop program counter off the stack
4. RETI : Pop program counter off the stack
: and reset interrupt hardware.
Chap3. Timer Interrupt & Optimize
Timer Interrupt
0FFF
PROGRAM
LOCATIONS
Longer service routines can be jump
instruction
002B
RI+TI
0023
TF1
INTERRUPT 001B
TABLE IE1 If an interrupt service routine is short
0013
enough ( as is often the case in control
TF0 8 BYTE
applications), it can reside entirely
000B
IE0 within that the 8-byte interval.
0003
RESET 0000
TCON Register
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
NAME Function
Timer x over flow Flag
Set by hardware on timer/counter overflow
TFx
Cleared by hardware
when processor vectors to interrupt routine
Timer x Run control bit

TRx
Set/Cleared by software to turn timer/counter on/off
TCON Register
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
NAME Function
Interrupt x Edge flag
IEx Set by hardware when external interrupt edge detected
Cleared when interrupt processed.
Interrupt 1 Type control bit

ITx Set/Cleared by software to specify
Falling edge/low level triggered external interrupts
TMOD Register - Operation Control
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
TIMER1 TIMER2
GATE Gating Control
When Set Timer/Counter “x”is enabled
Only while “INTx”pin is high and “TRx” control pin is set
When Cleared Timer “x” is enabled
Whenever “TRx” control bit is set
C/T Timer or Counter Selector
Cleared for Timer operation (input from internal system clock).
Set for Counter operation (input from “Tx” input pin)
TMOD Register - Operating Mode Control (0 , 1, 2 )
(MSB) (LSB)
TIMER1 TIMER2
M1 M0 Function
0 0 8048 TIMER : ”TLx” serves as 5-bit prescaler.
0 1 16-bit Timer/Counter : “THx” and “TLx” are cascaded
“THx” hold a value which is to be

1 0 Reloaded into “TLx” each time it overflows
TMOD Register - Operating Mode Control (Mode 3)
(MSB) (LSB)
TIMER1 TIMER2
Timer Function
TL0 is an 8-bit timer-counter

Controlled by the standard Timer 0 control bits
Timer 0
TH0 is an 8-bit timer
Only Controlled by Timer 1 control bits (TCON.TR1)
Timer 1 Timer-counter 1 stopped
Timer Mode - Mode 0
Timer/Counter 1 Mode 0:13-bit Counter

osc  12
C /T  0
TL1 TH1
TF1 INTERRUPT
(5BITS) (8BITS)
T1 PIN C / T  1 CONTROL
TR1
GATE
INT1 PIN
Timer Mode - Mode 1
Timer/Counter 1 Mode 1:16-bit Counter

osc  12
C /T  0
TL1 TH1
TF1 INTERRUPT
(8BITS) (8BITS)
TR1
GATE
INT1 PIN
Timer Mode - Mode 2
Timer/Counter 1Mode 2:8-bit Auto-Reload

osc  12
C /T  0
TL1
TF1 INTERRUPT
(8BITS)
RELOAD
TR1
TH1
GATE (8BITS)
INT1 PIN
Timer Mode - Mode 3
osc  12 Timer/Counter 0 Mode 3 : Two 8-bit Counters

C /T  0
TL0
TF0 INTERRUPT
(8BITS)
TR0
GATE 1/12 fOSC TH0

(8BITS) TF1 INTERRUPT
INT 0 PIN TR1

CONTROL
Vector Table (Single Board Case)
EXTERNAL PROGRAM
MEMORY (ROM) In Our Single - Board Case,
Actual interrupt service routine
0023 have to be exist in the data memory area
(RAM address range: 8000H ~ 9FFFH)
001B
LJMP 80F9H TF1
0013 LJMP 80F6H IE1

INTERRUPT VECTOR TABLE
LJMP 80F3H
000B
TF0
LJMP 80F0H IE0

0003
0000

8051

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

8051

Hochgeladen von

Copyright:

Verfügbare Formate

Micro-Controller 8051

주식회사 H.I 시스템

8031AH NONE 128x8 RAM 2 x 16 -Bit 5

OSCILLATOR ROM RAM TWO 16-BIT

64K BYTE BUS • PROGRAMMABLE

Ext INTERRUPTS CONTROL PARALLEL PORTS

Data Bit-Width 8 Bit

UART : Universal Asynchronous Receiver/Transmitter

Upper Address : 04h

EA : High : Internal Data Memory P0 : Address / Data I/O Port

ACCUMULATOR TEMP REG FLAG INSTRUCTION

ACCUMULATOR TEMP REG FLAG INSTRUCTION

ACCUMULATOR TEMP REG FLAG INSTRUCTION

Machine Cycle consists of six states ( 12 oscillator periods)

1-BYTE, 1-CYCLE Instruction (INC a ) READ NEXT OPCODE AGAIN

READ OPCODE READ NEXT OPCODE ( DISCARD)

2-BYTE, 1-CYCLE Instruction (ADD a , #data ) READ NEXT OPCODE

READ OPCODE READ 2nd BYTE

1-BYTE, 2-CYCLE Instruction (MOVX)

READ OPCODE NO FETCH NO FETCH

ACCESS EXTERNAL MEMORY

Logical Separation of Program and Data Memory

 After reset, the CPU begins execution from location 0000h

 The interrupt causes the CPU to jump to that location, where it

 The lowest 4K bytes of program memory can be either in the On-chip

Internal Program Memory : Lower 4KB region of the program memory

Longer service routines can be jump

The Lower 128 Byte of internal RAM

3rd REG. BANK

2nd REG. BANK

7F 7E 7D 7C 7B 7A 79 78 2Fh Boolean Instruction ( Bit Operation )

Ex) ANL CY, Bit Address

ANL CY, 27h.3

1. Software Control/Operation ( Acc, B, DPTR, PSW, SP )

 Acc : 8 Bit Accumulator ( Arith./Logical Operation)

 B : General Purpose Register : X , /

 DPTR : 16Bit Register , 8-bit accessable.

 PSW : 8 Bit -Register,

 SP : Stack Point , 8-Bit Register

(Specification of the Operation) (Specification of the Address)

The length of an Instruction depends on

Single-byte zero address Instruction

Single-byte two address Instruction

Two-byte one address Instruction

Three-byte one address Instruction

 Every general-purpose computer has its own unique instruction.

 Instruction (=Macro-Instruction) = The Sequences of Micro-Instruction

 1. The Immediate Addressing Mode

 The Immediate Addressing Mode

• Start Addressing : 8000h of external RAM

Ex ) Org 8000h ; set the origin

Org 8000h ; set the origin

Org 8000h ; set the origin

 The Direct Addressing Mode

Org 8000h ; set the origin

MOV ……. , ……..

Internal Data Memory  Acc, Reg ..

< Instr. Code >

PROGRAM DATA PROGRAM DATA

Org 8000h ; set the origin

 The Register Addressing Mode

MOV PSW, #00010000B ; BANK SELECT (BANK1)

MOV R3, #20h 1010 1011 0010 0000

MOV R0, R1 ; REG  REG (X)