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Introduction to Aging

EMICRO-NE 2017
IFCE – CAMPUS DE MARACANAÚ

26 a 28 de Agosto

Jardel Silveira e Caio Amaral


LESC
• R&D laboratory with full-time engineers and
• academics;
• Activities initiated in June, 2004;
• Part of the Department of Teleinformatics;
• Engineering (DETI)/UFC;
• Area: > 1000 m2.
Staff
• 5 professors/Ph.Ds/MSc , 19 development
engineers, more than 20 grad and post-grad
students, 2 secretary.
LESC (old)
LESC (new)
Hardware Skill
• Design of embedded systems: firmware & hardware
– ARM, OMAP, DSP, INTEL and AMD embedded processors and device drivers;
• Expertise on several embedded operating system:
– Linux( bootloader support, BSP, Kernel porting, hardware integration and test);
– Android (bootloader support, BSP, Kernel porting, system customization and test;
– Bare metal firmware (AVR, PIC, MSP430, ARM);
• Design of electronics (PCB) high-density multilayers boards;
– Conception;
– Schematics;
– Layout;
– Signal Integrity;
– BOM;
– AVL;
– Bring-up;
• Automation
• Real-Time Systems
• Microelectonics
• RFiD
Software Skill
• Computers: UEFI diagnosis and testing;
• Expertise on plant’s assembly line for several platforms e technologies:
– Personal computers diagnosis;
– Notebooks diagnosis;
– Server station diagnosis;
– Embeded diagnosis;
– Uefi diagnosis
• Porting of operating systems (including Linux, Windows, android) on to
embedded systems;
• Design of diagnosis and testing systems either embedded or for use at the
plant’s assembly lines;
• Android applications;
• Expertise on several architectures:
– X86, ARM, PowerPC
• Linux & Android-based systems.
• Digital Signal Processing;
LESC Aging Team
• Prof. Dr. Fabian Vargas (PUC-RS)
• Prof. Dr. Jarbas Silveira (UFC)
• Prof. Dr. Paulo Cortez (UFC)
• Prof. Msc. Jardel Silveira (UFC)
• Caio Amaral (Computer Engineering Student UFC)
• Saulo Mendes (Computer Engineering Student
UFC)
• Jorge Reis (Computer Engineering Student UFC)
• Danilo Coutinho (Computer Engineering Student
UFC)
Agenda
• LESC
• MOS
• Robustness
• Ring Oscillators
• Modelling
• FPGA
• Online Sensors
– Valdes, Sensible e Hans
– Automatic Insertion (xdl and path selection)
• Tests
– Voltage Scaling
– Burn in for Accelerated Aging
• XDL and Sensor Insertion
• Mitigation
Objectives
• Introduce the theme of integrated circuit
aging;
• Show some oportunities for research area of
integrated circuits aging, in particular of
FPGAs;
• Provide a few practical resources for a
beginner in aging Experimentation for FPGAs.
Main failure mechanisms of
an aging MOS transistor
• Negative-bias temperature instability (NBTI)
• Positive-bias temperature instability (PBTI)
• Hot Carrier Injection (HCI)
• Time-dependent dielectric breakdown (TDDB).

The effect of these failures is a change of the


threshold voltage of transistors, which causes a
degradation of the propagation time of logic gates.
Accelerated Lifetime Testing
• Expected reliability typically exceeds 10 years
• But products come to market in 1-2 years
• Accelerated lifetime testing required to
predict adequate long-term reliability
Hot Carriers
• Electric fields across channel impart high energies
to some carriers
– These “hot” carriers may be blasted into the gate
oxide where they become trapped
– Accumulation of charge in oxide causes shift in Vt over
time
– Eventually Vt shifts too far for devices to operate
correctly
• Choose VDD to achieve reasonable product
lifetime
– Worst problems for inverters and NORs with slow
input risetime and long propagation delays
NBTI
• Negative bias temperature instability
• Electric field applied across oxide forms
dangling bonds called traps at Si-SiO2 interface
• Accumulation of traps causes Vt shift
• Most pronounced for pMOS transistors with
strong negative bias (Vg = 0, Vs = VDD) at high
temperature
TDDB
• Time-dependent dielectric breakdown
– Gradual increase in gate leakage when an electric
field is applied across an oxide
– a.k.a stress-induced leakage current
• For 10-year life at 125 C, keep Eox below ~0.7
V/nm
Electromigration
• “Electron wind” causes movement of metal
atoms along wires
• Excessive electromigration leads to open circuits
• Most significant for unidirectional (DC) current
– Depends on current density Jdc (current / area)
– Exponential dependence on temperature

– Black’s Equation:

– Typical limits: Jdc < 1 – 2 mA / mm2


Shockley 1st order transistor
models

 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
Trap Detrap Model
Aging Effect and Digital
Circuits
High k Metal Gates
• Design and implementation of a low cost test
bench to assess the reliability of FPGA

• M. Naouss ⁎, F. Marc
• University of Bordeaux, IMS Laboratory UMR
5218, Bordeaux, France
• Journal Microelectronics Reliability
• Elsevier
• Qualis 2014 A2
• http://www.journals.elsevier.com/microelectroni
cs-reliability
• Article history:
Received 25 May 2015
Received in revised form 17 June 2015
Accepted 18 June 2015
Available online 2 July 2015
Setup Test Details
• PC running specific app developed by authors
• Altera Cyclone III 65 nm FPGAs including
10,320 LUTs.
• Arduino Due platform to create a network
between a PC host and up to 32 FPGAs
Setup Proposal
Ring Oscillators
Measuring Circuit
Stress Types
• Static
– DC0 – 0 constant
– DC1 – 1 constant
• Dynamic
– HF90 –High Frequency and Duty Cycle 90%
– HF10 - High Frequency and Duty Cycle 10%
– LF90 - Low Frequency and Duty Cycle 90%
– LF10 - Low Frequency and Duty Cycle 10%
Stress Types and Their
Influence
Burn-in for Accelerated
Aging
• -The procedure is described by automotive standard
AECQ-100 which refers to JEDEC Standard No. 22,
method A108D”TEMPERATURE, BIAS, AND OPERATING
LIFE” , and by MIL-STD 883 method 1005.9 “STEADY-
STATE LIFE”

• -In both standards different test conditions are
described, recommending for digital ICs the High
Temperature Operating Life (HTOL test). The standard
test condition are 1000 hours (more than 41 days) at
125°C, although an accelerated high temperature
condition is also described by the MIL-STD.
Burn-in for Accelerated
Aging
• Temperature: 125°C, allowing an error of -0°C and +8°C.
125°C < temperature < and 133°C. The uncertainty of +2°C
of the equipments at PUCRS is acceptable, and we should
request to use a nominal temperature of 127°C to take in
account the fluctuations in temperature of the oven.
• Duration:
– Standard: 41 days (1000hs) at 125°C
– Accelerated:
• 256hs (10 days 6 hs) at 145°C (145°C<temperature<153°C)
– 184hs (7 days and 16hs9 at 150°C (150°C<temperature<158°C)
• Bias: Circuits must be powered with the highest operating
voltage accepted in the datasheet.
Aging Sensors
Aging Sensors
Valdes
Sensible
Hans
Xilinx 7 Series FPGAs

Lowest Power Industry’s Best Industry’s Highest All Programmable


Maximum Capability and Cost Performance SoC
Price/Performance
Logic Cells in K
Block RAM in Mb
DSP Slices
Peak DSP Perf. (GMACs)
Transceivers

Transceiver Perf. (Gbps)

Memory Perf. (Mbps)


User I/O Pins

I/O Voltages
Artix 7 Architecture
XDL
TORC (ISE) e TINCR
(Vivado)
• TORC
– For Ise, because it´s input is na XDL file
– C++
– Requires Boost parser lib
– http://torc-isi.sourceforge.net/
• TINCR
– For Vivado
– TCL Based
TORC Structure