Optimization Techniques for

Digital VLSI Design

Module 4: VLSI Testing

Santosh Biswas
IIT Guwahati
 Course Plan

Module 4: VLSI Testing

Lecture 1 and 2: Introduction to Digital VLSI Testing, Automatic Test
Pattern Generation (ATPG), Design for Testability
Lecture 3: Optimization Techniques for ATPG
Lecture 4: Optimization Techniques for Design for Testability
Lecture 5: High-level fault modeling
Lecture 6: RTL level Testing
 VLSI Design, Verification and Test Flow
Customer's Requirements

Specifications Manual

Architecture Synthesis Scheduling

High Level Synthesis
Allocation/Binding

Verification of RTL design with Specifications

RTL Design

Front-end

Logic Synthesis

Verification of Logic circuit with RTL Design

Floor Planning
Back-end Physical Layout
Placement & Routing
Verification of circuit extracted from layout with logic circuit
VLSI Design, Verification and Test Flow

Test Planning

Fabrication

Manufacturing Test

Chips to Customers
Introduction to Philosophy of Testing
• “If anything can go wrong, it will”--A very well
known statement known as Murphy’s Law.
• Testing a system comprises subjecting it to
inputs and checking its outputs to verify
whether it behaves as per the specifications
targeted during design.
 Example: Electrical Iron
• Plug it in 220V AC and see if is heating.
– “functional” specification, that also partially.
• Safety:
– All exposed metal parts of the iron are grounded
– Auto-off on overheating
• Detailed Functionality
– Heating when powered ON.
– Glowing of LED to indicate power ON.
– Temperature matching with specification for different
ranges that can be set using the regulator (e.g.,
woolen, silk, cotton etc.)
 Example: Electrical Iron
• Performance
– Power consumption as per the specifications
– Time required to reach the desired temperature when
range is changed using the regulator
Tests for ONLY electrical parameters.
• Tests for mechanical parameters, like maximum
height from which there is resistance to breaking
of plastic parts if dropped on a tiled floor etc.
• Number of tests performed depends on the time,
equipments etc. which in turn is decided by the
target price of the product.
 Example: NAND Gate
v1

v2 o1

Input Output
v1 v2 o1
0 0 1
0 1 1
1 0 1
1 1 0
This test for the NAND gate is just the starting point
 Detailed tests for the NAND gate
• Digital Functionality
– Verify input/output of Table 1
• Delay Test
– 0 to 1: time taken by the gate to rise from 0 to 1.
• v1=1, v2=1 changed to v1=1, v2=0; After this change in
input, time taken by o1 to change from 0 to 1.
• v1=1, v2=1 changed to v1=0, v2=1; After this change in
input, time taken by o1 to change from 0 to 1.
• v1=1, v2=1 changed to v1=0, v2=0; After this change in
input, time taken by o1 to change from 0 to 1.
 Detailed tests for the NAND gate
– 1 to 0: time taken by the gate to fall from 1 to 0.
• v1=0, v2=0 changed to v1=1, v2=1; After this change in
input, time taken by o1 to change from 1 to 0.
• v1=1, v2=0 changed to v1=1, v2=1; After this change in
input, time taken by o1 to change from 1 to 0.
• v1=0, v2=1 changed to v1=1, v2=1; After this change in
input, time taken by o1 to change from 1 to 0.
• Fan-out capability:
– Number of gates connected at o1 which can be
driven by the NAND gate.
 Detailed tests for the NAND gate
• Power consumption of the gate
– Static power: measurement of power when the output of the
gate is not switching.
– Dynamic power: measurement of power when the output of
the gate switches from 0 to 1 and from 1 to 0.
• Threshold Level
– Minimum voltage at input considered at logic 1
– Maximum voltage at input considered at logic 0
– Voltage at output for logic 1
– Voltage at output for logic 0
• Test at extreme conditions
– Performing the tests at temperatures (Low and High
Extremes) as claimed in the specification document.

Tests are for the “logic level” of the NAND gate.

Detailed tests for the NAND gate
VDD

v1 v2
T1
-
T2
o1
Drain +
I DS
Body
v1 T3
VBS
VDS
Gate

v1 T4 VGS
Source
GND

Nmos (T3)
CMOS implementation for the NAND gate
 Detailed tests for the NAND gate
• Output Characteristics
– a set of IDS vs VDS curves for different constant values of
the gate-source voltage VGS
• Transfer characteristics
– a set of IDS vs VGS curves for different values of the
substrate-source voltage VBS, at constant VDS
• Threshold Voltage Test
– Threshold Voltage obtained in test, matches the
specifications
Detailed tests for the NAND gate

Layout of a NAND gate in a silicon die

 Optimal Quality of Test
• Given a digital logic gate, what tests are to be performed to assure
an acceptable quality of product at reasonable price”.

• Test for the NAND gate should be such that results are accurate (say
99% above) yet time for testing is low (less than a millisecond).
– Table 1 for the NAND gate and at proper time

• DIGITAL TESTING is not testing digital circuits (comprised of logic

gates).

DIGITAL TESTING is defined as testing a digital circuit to verify that it

performs the specified logic functions and in proper time.
 Digital VLSI test process

Circuit for Bit wise ANDing

Test Pattern Test Pattern Output

No.
1 0000000000000000000000000 0
2 0000000000000000000000001 0
………… …………………………………………….. 0
225 1111111111111111111111111 1

Test patterns for functional testing

 Introduction

•Need to apply 225 test patterns.

•1000000 patterns per second (Mega Hz Tester), time required is 33
Seconds per chip.
• About million chips are to be tested in a run

33000000 Seconds or 550000 Hours or 22916 Days or 62 years.

Functional Testing cannot be performed due to extremely high

testing time.
 Structural Testing

• Structural testing, introduced by Eldred, verifies the correctness

of the specific structure of the circuit in terms of gates and
interconnects

•Structural Testing takes many fold less time compared Functional

Testing yet maintaining the quality of test solution.

• Structural testing does not check the functionality of the entire

circuit rather verifies if all the structural units (gates) are fault
free. So structural testing is a kind of functional testing at unit
(gate) level.
Structural Testing Example

Test Pattern Output (OG1)

(I1,I2,I3,I4,I5)
1 00000 0
2 00001 0
… ….. 0
32 11111 1
 Structural Testing Example

• Number of test patterns required are 6.25

(=160), which is many fold smaller than those
required for functional testing (225).
• Time required for testing the circuit the using
a 1 Mega Hz Tester is 0.000016 seconds and
for a million samples is 16 seconds.
Structural testing is highly beneficial over
functional testing.
 Structural Testing—Penalties
• Each individual gate is tested; however, the
integration is not tested.
• To test the individual gates, controlling and
observing values of intermediary nets in a circuit
becomes mandatory, which adds to extra pins
and hardware
• Circuit with about a million internal lines needs a
million 2-1 Multiplexers and same number of
extra pins. This requirement is infeasible.
Structural Testing—Penalties
 Structural Testing with Fault Models
• Unconnected net I1 is the defect.
• Error is, when I1=1, I2=1,I3=1,I4=1, I5=1 but OG1=0
(should be 1 in normal case).
• Fault is, net I1 is stuck at 0 (when gate is modeled at
binary logic level).
 Types of Fault Models
• Stuck-at fault model: Faults are fixed (0 or 1)
value to a net. Stuck at-0 and Stuck at-1
– single stuck-at fault model
– Multiple stuck at fault model
• Delay fault model: Increase the input to
output delay of one logic gate, at a time.
• Bridging Fault: A short between a group of
nets
– AND Bridge
– OR Bridge
 Single Stuck-at Fault Model: Fanouts

If fanout along with all its branches is a single electrical net,

then why fault in a branch does not affect the others ?

•Only one net is faulty at a time.

•The faulty net is permanently set to either 0 or 1.
•The branches of a fanout net are independent with respect to
locations and affect of a stuck-at fault.
 Single Stuck-at Fault Model

•Several stuck-at faults can be simultaneously present in

the circuit.
•A circuit with n lines can have 3n-1 possible stuck line
combinations; each net can be: s-a-1, s-a-0, or fault-
free.
•Handling multiple stuck-at faults in a typical circuit with
some hundreds of thousands of nets is infeasible.

Single stuck-at fault model is manageable in number and

also provides acceptable quality of test solution, it is the
most accepted fault model.
Structural Testing with Stuck-at Fault Model

I1=1, I2=1,….,I25=1, is a
test pattern for the stuck-
at-0 fault at net I1
Structural Testing with Stuck-at Fault Model

I1=0, I2=1,….,I25=1, is
a test pattern for the
stuck-at-1 fault at net
I1.
Structural Testing with Stuck-at Fault Model

I1=0, I2=1,….,I25=1, is a
test pattern for the stuck-
at-1 fault at net output
of G1.

I1=0, I2=1,….,I25=1 tests

both s-a-1 at net I1 and
output of G1.

In structural testing with

stuck-at fault model, one
test pattern can test
more than one fault.
Pros and cons for structural testing with stuck-at
fault model
• Pors
– No extra pin outs or DFT circuitry like 2-1 Multiplexers
and shift resisters for controlling and observing internal
nets
– Low test time as one test pattern can test multiple
stuck-at faults
• Cons
– Functionality is not tested, even for the units (gates and
Flip-flops). However, testing history reveals that even
with this price paid, quality of test solution is
maintained.
Automatic Test Pattern Generation:
Fault Simulation
 Path Sensitization Based ATPG
ATPG by path sensitization method is generally applied for “difficult to test
faults” and comprises three phases.

Fault sensitization: In this step a stuck-at fault is activated by setting the

signal driving the faulty net to an opposite value from the fault value.

Fault propagation: In this step a path is selected from the fault site to some
primary output, where the effect of the fault can be observed for its
detection.

Line justification: In this step the signals in (internal) nets or some primary
inputs, which were assigned for fault sensitization/propagation, are
justified by setting (remaining) primary inputs of the circuit.

In the second and third steps, a conflict may occur, where a necessary
signal assignment contradicts some previously-made assignment. When
conflicts occur we need to take a new alternative path for fault propagation
and see if all signals can be justified.
 Roth’s five value algebra

Symbol Implication Normal Faulty

Circuit Circuit
0 (0/0) 0 0

1 (1/1) 1 1

X (X/X) X X

D (1/0) 1 0

(0/1) 0 1
 Example to illustrate Roth’s five value algebra

1
I1
D (Normal: 1, Fault: 0)
G1 0
1 (s-a-1)
I2 O1 (s-a-0) I1
X (Normal: X, Fault: X)
G1
X
I2 O1
0
I1
D (Normal: 0, Fault: 1)
G1
0
I2 O1 (s-a-1)
Path Sensitization Based ATPG: Example
a f
D
e D
b=1 g D
h
s-a-0
i j
D
c

(a) Sensitization by b=1

Propagation by path e-f-g-h

a f
D
e D
b=1 g D
h
s-a-0
i D j 0
D
c

d=1

(b) Justification j=0

j=D, if c=1 and j=1 if c=0
(conflict at j)
 Path Sensitization Based ATPG: Example
a f

e
b=1 g D
h
s-a-0
iD j D
c
D
d

(a) Sensitization by b=1

Propagation by path i-j-g-h

a=0 f
0
e
b=1 g D
h
s-a-0
iD j D
c=1
D
d=1

(b) Justification d=1,c=1,f=0,a=0

(Successful)
What about Sequential Circuits
 ATPG of sequential circuits: Example

c
a e
s-a-0
f 1
d Q
2 D
b

clock
primary output g

A simple sequential circuit with a stuck-at-0 fault

 ATPG of sequential circuits: Example

D c
a=1 e
s-a-0 X
f 1
d Q
2 D
b=X

clock
primary output g
X

Problems in ATPG for the stuck-at-0 fault

 ATPG of sequential circuits: Example

D c
a=X e
s-a-0 X
f 1
d Q
X 2 D
0
b=0

clock
primary output g
X

Indirect controlling of f to 0
 ATPG of sequential circuits: Example

D c
a=1 0 e
s-a-0 0
f 1
d Q
0 2 D
b=X

clock
primary output g
D

Test pattern for the s-a-0 fault

ATPG for combinational blocks in sequential circuits require more than one pattern.
In this example, the first pattern is a=X, b=0 and clock edge followed by a=1 and
b=X.

Final pattern is according to combinational ATPG (that sensitize the fault and
propagates the effect to a primary output) and all other initial patterns are to bring the
secondary inputs to their required value.
 Controllability and observability of flip-flops
•Set and reset lines
One of the simplest way to directly control flip-flops is through set-reset lines. Set-
reset lines can directly make the output of a flip-flop to be 1/0 without any input
and clock pulse. set
input
D Q

clock
reset

Input (D) Output (Q) set reset clock

Don’t care 1 1 0 Don’t care
Don’t care 0 0 1 Don’t care
Don’t care Illegal 1 1 Don’t care
1 1 0 0 Clock edge
0 0 0 0 Clock edge
 ATPG : Controllability and observability of flip-flops
•By D-algorithm, a test pattern would be: primary input =0, secondary input
(other input of XOR gate)=0 and fault effect at primary output=D.
•So in Step-1, set=1 and reset=0 (and primary input =X); this makes output of flip-
flop (i.e., secondary input) to be 1.
 ATPG : Controllability and observability of flip-flops
•In Step-2, set=0, reset=0 and primary input =0; this sensitizes fault location as
and its effect propagates to the input of the flip-flop as D. Also a positive clock
pulse is applied which transfers D to output of the flip-flop (primary output).
These two steps complete ATPG (and testing) of the fault.
Scan Chain based Testing and ATPG for sequential circuits

normal input from NSF Q

D
Mux Scan out

Scan in
mode

A scan flip-flop

normal input
NI
Scan out
Scan Flip SI Q
Scan in
Flop Scan Flip
Q
Flop

clock clock
mode M

Block diagram of a scan flip-flop

 Scan Chain based Testing and ATPG for sequential circuits

D Q Scan out
normal input from NSF Mux secondary inputs (An additional output)

Scan in clock
mode

Scan out
D Q
normal input from NSF
Mux secondary inputs

clock
Scan in
mode

Scan out
normal input from NSF D Q
Mux secondary inputs

clock
Scan in
(An additional input) mode
 Scan Chain based Testing and ATPG for sequential circuits
Flip-flops in scan chain mode

D Q Scan out
normal input from NSF Mux secondary inputs (An additional output)

Scan in clock
mode=1

Scan out
D Q
normal input from NSF
Mux secondary inputs

clock
Scan in
mode=1

Scan out
D Q
normal input from NSF
Mux secondary inputs

clock
Scan in
(An additional input) mode=1
Scan Chain based Testing and ATPG for sequential circuits
Flip-flops in normal mode

D Q Scan out
normal input from NSF Mux secondary inputs (An additional output)

Scan in clock
mode=0

Scan out
D Q
normal input from NSF
Mux secondary inputs

clock
Scan in mode=0

normal input from NSF Scan out

D Q
Mux secondary inputs

clock
Scan in
(An additional input) mode=0
 ATPG and testing using scan chain : An Example

The sequential circuit (running example) now with scan chain--To test
the s-a-0 fault at net j, the signal values at nets d and i are to be 1.
 ATPG and testing using scan chain : An Example
So both the flip-flops are to be set to 1; this was achieved by making the set input
as 1 and reset input as 0 in case of testing using set/reset flip-flops.

In case of scan chain, to set the flip-flops,

•Making M=1, removes the next state function block from the circuit and the flip-
flops are connected in a chain
• Two 1s are applied in the Scan in input at two clock pulses which makes d=1
and i=1.
 ATPG and testing using scan chain in a sequential circuit:
An Example

•Circuit is brought in normal mode by making M=0. In this stage testing is

performed by making a=1,b=1,c=X which propagates the fault effect to the
output
Thank You