ULTRA STEP-UP DC-DC

CONVERTER WITH REDUCED

SWITCH STRESS
Group Members:
Akshay Vishnu
Nived Soman
Athira D.S
Drishya Dinesh
Saptha Balan
Under the Guidance of:
Arathi.M.Nair
A.P EEE
CONTENTS
 INTRODUCTION
 SOFTWARE REQUIREMENTS
 HARDWARE REQUIREMENTS
 CONVERTER DESIGN
 INDUCTOR DESIGN
 CIRCUIT DIAGRAM
 CIRCUIT OPERATION
 SIMULATION RESULT
 HARDWARE MODEL
 OBESERVATIONS
INTRODUCTION
 A step-up converter is also known as Boost converter.
 It step-up voltage from its input to the output.
 By practical considerations, the output of a conventional boost converter is limited to
approximately six times the applied voltage.
 Inoder to supply a high output voltage with better efficiency by reducing both switching
and conduction losses, we use high step up converter topology.
 The cascade boost converter can meet the requirements of supplying a high output
voltage with a relatively high efficiency. The major drawbacks of this solution are the
complexity and higher cost resulting from using two dc–dc converters. The two power
switches in the cascade converter must be synchronized to avoid the beat frequency, and
the stability of the converter is also a concern.
 Quadratic converters can provide large step-up voltage conversion ratios. But, the switch
voltage stress in quadratic converters is equal to the output voltage. Thus, no advantage
over the conventional boost converter is achieved.
 These drawbacks associated with existing high step-up boost converters
encourage a search for a high step-up converter topology which enables the use
of a lower voltage rated and lower RDS−ON MOSFET in order to provide better
efficiency by reducing both conduction and switching losses.
 Here, a new single switch nonisolated dc-dc converter with high voltage transfer
gain and reduced semiconductor voltage stress is proposed.
 This topology uses a hybrid switched capacitor technique. This provides a high
voltage gain at moderate duty cycle.
 To reduce the MOSFET stress, a lower voltage rated and lower RDS-ON MOSFET is
used as the switch to reduce cost, switch conduction and turn-on losses.
SOFTWARE REQUIREMENTS
 MP LAB:
Its used to provide a delay program for the turn on and turn off of
MOSFET switch. The program is then burned to PIC16F877A.
 MATLAB SIMULINK:
Simulink is used to verify the circuit accuracy and obtain the
approximate output with the proposed circuit.
HARDWARE REQUIREMENTS

 CAPACITOR: 68μF
 INDUCTOR: 207.6μH
 LOAD RESISTOR: 260Ω
 MOSFET STP75NF75:
Its specifically designed to minimize input capacitance and gate
charge. It is therefore suitable as primary switch in advanced high
efficiency, high-frequency isolated DC-DC converters for Telecom and
Computer applications. It is also intended for any applications with low
gate drive requirements.
 DIODE 1N4001:
It’s a rectifying device that conducts only from anode to cathode. Diode
1N4001 is a 1A diode with low forward voltage drop and high surge current
capability.

 DC SOURCE:
The input voltage is fixed to 3V. So we give 3V DC supply using two 1.5V
battery.

 PIC 16F877A:
PIC 16F877A is a 40pin IC. Delay program that was successfully build
in MP LAB is burned into this IC.
 VOLTAGE REGULATOR 7805:
Voltage regulator IC maintains the output voltage at a constant value.
7805, a voltage regulator integrated circuit (IC) is a member of 78xx series of
fixed linear voltage regulator ICs used to maintain such fluctuations. The xx in
78xx indicates the fixed output voltage it provides. IC 7805 provides +5 volts
regulated power supply with provisions to add heat sink as well. Its used here
to give 5V supply to
 CRYSTAL OSCILLATOR:20MHz

 RESISTOR: 10KΩ
 CAPACITOR:22pF
 9V DC SUPPLY
CONVERTER DESIGN:
The design of the converter is done under the assumption that
1)Converter is operating in continuous conduction mode.
2)All the circuit components are ideal.
3)Input voltage is constant.
4)Output capacitor is large enough to keep the output voltage constant.
Also let
a) D is the duty ratio and Ts is the switching period
b) La=Lb, Ca= Cb
Here 30W prototype of the proposed converter is designed by considering
an input of 12V, with switching frequency 80 kHz and
duty ratio D as 0.692.
For Vin = 12V with a conversion ratio of 12
The output vol tage Vo = 144V
Po  Vo  Io
Po 30
Io    0.208A
Vo 144
Under the assumption of ideal condition we can take
input power, Pin = output power, Po
Vin  Iin  Vout  Iout
(Vout  Iout) (144  0.208)
Iin    2.5A
Vin 12
Vo 144
The load resistance , Ro    692.3 
Io 0. 208
take Ro  260 
diL
We have , VL  L  Vin
dt
L  Vin  D  Ts
Let inductor current ripple be 1A.
1
T  10  4 sec
10  10 3

L  3  0.692  10  4  207.6 H
The capacitors can be designed as follows :
Let the peak to peak ripple in output vol tage be 0.05%of output vol tage.
The proposed converter is a boost converter with capacitor diode voltage multiplier .
The formula for output capacitor can be written as
DTs 0.692  12.5  10 6
C   24  10 6 F
R  0.005 692  0.0005
C  24 F
Take Ca  Cb  Cin  Cf  33F
INDUCTOR DESIGN:
L  207.6 H
let iL  10% of Io  0.1 0.1389  0.01389A
iL 0.01389
Im  Io   0.1389   0.146 A
2 2
1 1
EL  L Im 2   207.6  10 6  0.146 2  2.21 10 6 J
2 2
2 EL
Ap  AwAc 
KwKcJBm
let Bm  0.27T for ferrite
J  3  10 6 A / m 2
Im 0.146
Kc    1.05
Io 0.1389
Kw  0.6
2  2.21 10 6
Ap   9.35  10 12 m 4  9.35mm4
0.6  1.05  3  10 6  0.25
from data sheet, E 20/10/15 EE core is selected.
Ap  1481mm 4 , Aw  47.8mm4 , Ac  31mm4 , lm  42.8mm
mean length per turn  38mm
to calculate permeance, relative permeabili ty has taken from data sheet,
r  2000  25%
herer  1500
let airgap length  0.5mm
orAc 4  10 7  1500  3.1 10 6
    7.37  10 8 H / mm2
lm  rlg 42.8  10 3  1500  0.5  10 3
L 207.6  10 6
N   2816.82
 7.37  10 8
N  53.07
take N  54turns
wire guage,
Irms 0.1389
area of cross section of wire, a    4.63  10 8
J 3  10 6

a  0.0463mm2
 SWG  33(selected from data sheet, for a  .050670mm 2 )
Circuit diagram
Circuit operation
 The figure shows proposed ultra step-up DC-DC converter with reduced switch
stress.
 When the switch Q is open, the capacitor C1 and C2 are in parallel an hence they
are equally charged by the energy stored in the inductor. Diodes D01 and D02 are
forward biased in this case.
 When switch Q is closed, C1 and C2 discharges in series through load and input.
D01 and D02 are reverse biased here.
 The operation of the circuit is explained by two modes.
1.Continuous conduction mode(CCM)
2.Discontinuous conduction mode(DCCM)
Continuous conduction mode(CCM)
 When the converter operates in CCM, the current ripples through L1 and L2 are
assumed as negligible.
 One switching cycle can be divided into two stages.
STAGE 1:
 When the power switch Q is turned on, the diodes D1, D2 and D3 are turned on
simultaneously and D01 and D02 are turned off by a negative voltage (Vc1-Vo)
across them.
 Voltage across L1, L2 and C are same and equal to input voltage Vg.
 The voltage (Vo−Vg) is divided equally between the two capacitors C1 and C2.
 Here C1 and C2 charges the load whereas Vg charges C.
 Q is turned off at the end of this sub interval.
STAGE 2:
 At time t1, switch Q is turned off.
 Both diodes Do1 and Do2 are turned on simultaneously, providing a path for the
inductor currents iL1 and iL2.
 DiodeD3 is reversed biased by the negative voltage (VC1 −Vo) across it, while D1
and D2 are reversed biased by the negative voltage (−VC1−VC)/2 across them.
 In this stage, the two capacitors C1 and C2 are effectively in parallel; hence, they
are being charged equally.
 The voltages across inductors L1 and L2 are also the same, and it is equal to (VC
−VC1)/2.
 They can be magnetically coupled into a single magnetic core. As a consequence,
the size, the cost, and the power loss of the magnetic devices are greatly reduced,
allowing higher power density as compared to using two separate inductors.
Discontinuous conduction mode(DCM)
SIMULATION RESULT
OBSERVATIONS
 The converter has a voltage gain of around 12 and the switch voltage is only one half of
the output voltage during off condition.