Guided by: Presented by:

Ms. Anu Susan Philip, Aiswarya Nair B.

Asst. Professor, Fasima R.S.
Dept. of ECE, Libya Thomas
MBCET Visakh V.

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OVERVIEW:
1. Introduction
2. Need for ETA
3. Proposed Addition Arithmetic
4. Block Diagram
5. ETA
6. Inaccurate Part
7. Accurate Part
8. Experimental Setup
9. Application
10.Conclusion
11.References

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In modern VLSI technology, the occurrence of all kinds of errors has become
inevitable. By adopting an emerging concept in VLSI design and test, error
tolerance (ET), a novel error-tolerant adder (ETA) is proposed.
The ETA is able to ease the strict restriction on accuracy, and at the same time
achieve tremendous improvements in both the power consumption and speed
performance.

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 Huge data sets and the need for instant response require the adder to be
large and fast.

 ETA can attain great improvement in both the power consumption and
speed.

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Hardware implementation of ETA

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Accurate part
Constructed using a CONVENTIONAL ADDER such as
RCA,CSK,CSL, or CLA

Inaccurate part
Constitutes 2 blocks:

* Carry Free Addition Block

* Control Block

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Inaccurate part :

 Control Block

 Carry-Free Addition Block

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 The carry-free addition block is made up of 20 modified XOR gates, and
each of which is used to generate a sum bit

Architecture of Carry-Free Addition Block

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In the modified XOR gate, three extra transistors, M1, M2, and M3, are added to
a conventional XOR gate.
 When CTL=0 =>M1, M2 on, while M3 off, leaving the circuit to operate
in the normal XOR mode.
 When CTL=1 => M1,M2 off, while M3 on, connecting the output node to
VDD, and hence the sum output to “1.”

Schematic Diagram of a Modified XOR Gate

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 It is made up of control signal generating cells (CSGCs)
 Each cell generates a control signal for the modified XOR gate at the
corresponding bit position in the carry-free addition block.
 Instead of a long chain of 20 cascaded GSGCs, the control block is
arranged into five equal-sized groups, with additional connections
between every two neighboring groups.

Overall Architecture of Control Block

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Control Block
 Two types of CSGC, labeled as type I and II
 The control signal generated by the leftmost cell of each group is
connected to the input of the leftmost cell in next group.
 The extra connections allow the propagated high control signal to
“jump” from one group to another instead of passing through all the
20 cells.

Schematic Implementations of CSGC

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RCA(Ripple Carry Adder)
 Ripple-carry adder – the simplest and most compact parallel adders –
require as little as four cells per bit, and one layout has a carry delay of
only one cell per bit.

Block diagram of RCA

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CLA(Carry Look Ahead Adder)
 A carry look-ahead adder improves speed by reducing the
amount of time required to determine carry bits.
 It can be contrasted with the simpler, but usually slower, ripple
carry adder for which the carry bit is calculated alongside the
sum bit.
 Each bit must wait until the previous carry has been calculated
to begin calculating its own result and carry bits.

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 A carry-select adder achieves speeds 40% to 90% faster by performing
additions in parallel and reducing the maximum carry path.

Carry-Select Adder
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 The design of a carry skip adder that achieves low power dissipation and high-
performance operation.
 The carry skip adder’s delay and power dissipation are reduced by dividing the
adder into variable-sized blocks that balance the delay of inputs to the carry
chain.
 This grouping reduces active power by minimizing extraneous glitches and
transitions.

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 To demonstrate the advantages of the proposed ETA, we
simulated the ETA along with four types of conventional
adders, i.e., the RCA, CSK, CSL, and CLA, using Xilinx.

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 DSP applications related to the human senses
 Image Processing Systems
 Speech Processing Systems

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 In image processing and many other DSP applications, fast Fourier
transformation (FFT) is a very important function. The computational process of
FFT involves a large number of additions and multiplications.

 It is therefore a good platform for embedding our proposed ETA. To prove the
feasibility of the ETA, we replaced all the common additions involved in a
normal FFT algorithm with our proposed addition arithmetic.

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 The error-tolerant adder, which trades certain amount of accuracy for significant
power saving and performance improvement, is proposed.
 Extensive comparisons with conventional digital adders showed that the proposed
ETA outperformed the conventional adders in both power consumption and speed
performance.
 The potential applications of the ETA fall mainly in area where there is no strict
requirement on accuracy or where super low power consumption and high-speed
performance are more important than accuracy.
 One example of such applications is in the DSP application for portable device
such as cell phones and laptops.

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•DESIGN AND IMPLEMENTATION OF FIELD PROGRAMMABLE GATE ARRAY
BASED ERROR TOLERANT ADDER FOR IMAGE PROCESSING APPLICATION
N.Suganthi, M.E., Sr.Lecturer/ECE,Adhiparasakthi Polytechnic College,
Melmaruvathur-603319.
•Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion

Input Method Meenu Pareek1 , Manish Singhal2 1 M.Tech. Scholar , 2 Associate

Professor, Dept. of Electronics and Communication Poornima College of
Engineering, Jaipur, India
•Analysis of Low Power, Area- Efficient and High Speed Fast Adder Pallavi Saxena1 ,

Urvashi Purohit2 , Priyanka Joshi3 PG Scholar, Department of ECE, Mody Institute

of Technology and Science, Lakshmangarh, India2 Assistant Professor, Department
of ECE, Mody Institute of Technology and Science, Lakshmangarh, India 3

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