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EE 445L – Embedded System Design Lab

Architecture
Interfaces
Data flow graphs
Flowcharts
Fixed-point numbers

EE 445L – Bard, Valvano 1


EE 445L – Bard, Valvano 2
Embedded Systems
• An interface:
– is the hardware and software that combine to allow
the computer to communicate with external
hardware
– it must be able to adapt to a wide range of inputs
and outputs that can exist in either digital or analog
form

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Data Flow Graph
Systems
Lab 3 Alarm clock - Components
- Interfaces
push switch LCD
buttons interface LCD
interface hardware
main
logic
timer timer speaker
hardware interface speaker
interface hardware

Circles
- Software components Arrows
Rectangles - Data format
- Hardware components - Data bandwidth
EE 445L – Bard, Valvano - Data direction 4
Lab 4 Integral Controller

Motor Controller Data Flow Graph


Speed Voltage Threshold Freq Timer
Sensor Detect
100Hz 100Hz 100Hz
Capture
Motor Digital
Digital sample
Power PWM
Actuator Interface control 100Hz
100Hz 100Hz
100Hz Timer
Routines
ASCII Measured
Keypad Desired
Keypad Interface Routines speed speed
5Hz
5Hz 1Hz 100Hz
ASCII Controller Table
Speeds Software
LCD Interface LCD lookup
60Hz Routines 60Hz
60Hz
Circles
- Software components Arrows
Rectangles - Data format
- Hardware components - Data bandwidth
EE 445L – Bard, Valvano - Data direction 5
Memory Mapped Processor
Architecture
• In a system with memory mapped I/O
– I/O devices are connected like memory
– I/O devices are assigned addresses
– software accesses I/O using these addresses
– software inputs from an input device
• same instructions as a memory read
– software outputs from an output device
• same instructions as a memory write

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Memory Mapped Processor
Architecture
Microcontroller System bus
ARM® CortexTM-M
processor
Input
PPB ports
Internal
Advanced
peripherals High-perf Output
Bus ports
Instructions
Flash ROM Data
ICode bus DCode bus RAM
TM4C123
0x0000.0000 256 KiB
∙∙∙ Flash
0x0003.FFFF ROM

0x2000.0000 32 KiB
∙∙∙ Static
0x2000.7FFF RAM EE 445L – Bard, Valvano 7
Memory Mapped Processor
Architecture
• The bus contains:
– address (input, output, RAM or ROM),
– data
– control information
• The address specifies:
– which slave module will communicate with the
processor
– one address per memory access cycle

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Memory Mapped Processor
Architecture
• The data contains
– information that is being transferred.
• Control signals specify
– the direction of the transfer.
• We call a complete data transfer a bus cycle.
The processor always controls
– the address (where to access),
– the direction (read or write), and
– the control (when to access.)

EE 445L – Bard, Valvano 9


Memory Mapped Processor
Basic bus cycles Architecture
Type Address Driven by Data Driven by Transfer
Read Cycle Processor RAM, ROM or Input Data copied to processor
Write Cycle Processor Processor Data copied to output or RAM

Computer Bus

Processor
Input Input
ports External Physical signals
RAM circuits devices
Output Output
ports signals
ROM
Control
Address
Data

For more information read Section 1.1 in the book

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TM4C123 Architecture
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B


PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
PC7 GPIO Port C GPIO Port D PD7
PC6 PD6
PC5 USB 2.0 Twelve PD5
PC4 Timers PD4
PC3/TDO/SWO PD3
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0

GPIO Port E GPIO Port F


PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus


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TM4C1294 Architecture
1024k Cortex M4 256k
ROM RAM

8 4
Port A Port H
Eight Ten
6 UARTs I2Cs 2
Port B Port J

Four Two 8
4 SSIs CANs Port K
4 Port C
JTAG 8
Eight Port L
8 PC3-PC0 Timers
Port D
8
USB 2.0 Port M
Ethernet
6
Port E
6
ADC Port N
5 2 channels Three Analog
Port F 20 inputs Comparators 6
12 bits Port P
Eight PWM
2 outputs 5
Port G Port Q
Advanced High System Advanced High
Performance Bus Bus Performance Bus
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Interfaces
• Asynchronous Serial Communications
Interface (UART)
– Interaction between PC/TM4C
– Microcontroller network
• ADC systems are available with a 12-bit
precision

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Interfaces
• The Synchronous Serial Interface (SSI)
– Shift registers
– Organic Light Emitting Diode (OLED)
– ST7735 Liquid Crystal Display (LCD)
– Analog to Digital Converters (ADC)
– Digital to Analog Converters (DAC)
– Other microprocessors

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Interfaces
• The timer features on the TM4C:
– Fixed periodic rate interrupts
– Pulse Width Modulated outputs (PWM)
– Event counter system for advanced timing
operations
– Input capture used for period and pulse width
measurement
– Output compare used for generating signals and
frequency measurement

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Isolated I/O Processor Architecture
• Separate bus and instructions implement I/O:
– differentiates transfers of information with external
devices from those internal to the device
– provides a level of protection from problems
caused by software malfunction
– example: Intel x86 family

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Cortex M Architecture
Processor ICode bus
Registers Bus interface unit DCode bus
R0
System bus
R1 Private peripheral bus
R2 Advanced high-performance bus
--- Control unit ALU
SP
PC IR

R0
R1
R2 Special registers
R3
R4 PSR Program status register
General R5 PRIMASK
purpose R6 FAULTMASK Exception mask registers
registers R7 BASEPRI
R8 CONTROL CONTROL register
R9
R10
R11
R12
Stack pointer R13 (MSP) R13 (PSP)
Link register R14 (LR)
Program counter R15 (PC)

EE 445L – Bard, Valvano 17


Cortex M Architecture
31 30 29 28 27 0
APSR N Z C V Q Reserved
31 8 0
IPSR Reserved ISR_NUMBER
31 26 25 24 15 10 0
EPSR Reserved ICI/IT T Reserved ICI/IT Reserved

31 30 29 28 27 26 25 24 15 10 8 0
PSR N Z C V Q ICI/IT T Reserved ICI/IT ISR_NUMBER
APSR contains the current state of the condition
flags from previous instruction executions
IPSR contains the exception type number of the
current Interrupt Service Routine (ISR)
EPSR contains the Thumb state bit and the execution
state bits for the If-Then (IT) instruction

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Little endian memory access

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TI Microcontrollers
Labs
7,11
Part number RAM Flash I/O I/O modules
LM3S811 8 64 32 PWM
LM3S1968 64 256 52 PWM
LM3S2110 16 64 40 PWM, CAN
LM3S3748 64 128 61 PWM, DMA, USB
LM3S8962 64 256 42 PWM, CAN, Ethernet, IEEE1588
Launch
LM4F120H5QR 32 256 43 floating point, CAN, DMA, USB Pad
TM4C123GH6PGE 32 256 105 floating point, CAN, DMA, USB, PWM
TM4C123GH6PM 32 256 43 floating point, CAN, DMA, USB, PWM
TM4C123GH6ZRB 32 256 120 floating point, CAN, DMA, USB, PWM
TM4C1294NCPDT 256 1024 90 floating point, CAN, DMA, USB, PWM, Ethernet
KiB KiB pins

Connected
LaunchPad
For more information read Sections 2.1-2.4 in the book

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Fixed point numbers
• Why:
express values with non-integer values
no floating point hardware support

• When:
range of values is known
range of values is small

• How:
1) variable integer, called I.
may be signed or unsigned
may be 8, 16 or 32 bits (precision)
2) fixed constant, called  (resolution)
value is fixed, and can not be changed
not stored in memory
specify this fixed content using comments
EE 445L – Bard, Valvano 21
Fixed point numbers
• The value of the fixed-point number:
fixed-point number  I•

• Decimal fixed-point, =10m


decimal fixed-point number = I • 10m
nice for human input/output

• Binary fixed-point, =2m


binary fixed-point number = I • 2m
easier for computers to perform calculations

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Fixed point numbers
• How to design a fixed-point number?
– integer can be signed or unsigned
– precision is the number of distinguishable
values that can be represented.
• determined by the number of bits used to store the
variable integer, e.g., 8 bits or 16 bits
– resolution is the smallest difference in value
that can be represented.
• equal to the fixed constant (Δ).
• defines units
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Fixed point numbers
• Example Temperature Measurement System (Lab 9)
– Analog to digital converter (ADC)
– 12-bit precision (4096 alternatives, about 3 3/4
decimal digits)
– analog input range is 0 to +3.3 V,
– resolution = range/precision less than 1 mV
– digital output varies 0 to 4095.
• Measurement System
– range is 10 to 40 °C
– 12-bit precision
– resolution less than 0.01 °C

EE 445L – Bard, Valvano 24


Fixed point numbers
• Voltage representation
– Vin = 3.3 * N/4096 = 0.000805664 * N
• Temperature representation
– let T = 10+(30°C*Vin/3.3V) =10+9.09(°C/V) * Vin
– then T = 1000+3000*N/4096 where Δ is 0.01°C
• Representations of 0.732421875
– 0.732421875
– 73242/100000
– 3000>>12
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Fixed point numbers
• Issues (Δ=0.01°C)
– overflow
• I = 1000+(3000*N)/4096;
• reduce integer size
• promote to higher precision
– I = 1000+(3000*(unsigned long)N)/4096
– dropout
• I = 1000+3000*(N/4096);

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Fixed point numbers
• C optimization
– I = 1000+(375*N)/512;
– I = 1000+(375*N)>>9;

• Rounding
– I = 1000+(375*N+256)>>9;

• Assembly Optimization
Convert unsigned long Convert(
MOV r1,#375 unsigned long adc){
MUL r0,r1,r0 return 1000+(375*adc+256)/512;
ADD r0,r0,#256 }
LSR r0,r0,#9
ADD r0,r0,#1000
BX lr

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Fixed point numbers
• Consider the following digital filter
calculation:
y = x - 0.0532672*x1 + x2
+ 0.0506038*y1 - 0.9025*y2;
• The fixed-point implementation of this
digital filter is:
y = x + x2
+(-14*x1+13*y1 -231*y2)/256;

EE 445L – Bard, Valvano 28


Fixed point numbers
• Internal Data (contains all information)
– Δ=0.01°C e.g., 23.13°C stored as 2313
• Output LCD Display (honest, but some
data is discarded)
– Δ=0.1°C e.g., 23.1°C
• Output LCD Display (a little bit dishonest)
– Δ=0.01°C e.g., 23.13°C
Assume noise is
• Output LCD Display (honest) 0.03 °C
– Δ=0.01°C e.g., 23.13°C (±0.03°C)
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