Chapter 2:

MOS
Transistor
Theory
1. MOS transistor operation
2. I-V characteristics
3. C-V characteristics
4. DC transfer characteristics

2: MOS Transistor Theory 1

1. MOS Transistor Operation
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 2

 MOS Capacitor
 Gate and body form MOS
capacitor polysilicon gate

 Operating modes
V <0 g
silicon dioxide insulator
+
- p-type body
– Accumulation
– Depletion (a)

– Inversion 0<V <V g t

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 3

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

 Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 4

 nMOS Cutoff
 No channel
 Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 5

 nMOS Linear
 Channel forms
 Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
 Ids increases with Vds s d
Vds = 0
n+ n+
 Similar to linear resistor p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 6

 nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 7

 2. I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 8

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = CoxWL Cox = eox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 9

 Channel Charge
 MOS structure looks like parallel
plate capacitor while operating in
inversion:
 Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = coxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt

cox = eox / tox

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 10

 Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = mE m called mobility
 Time for carrier to cross channel:
– t=L/v

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 11

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs  ds
 2 
t
L
W
  Vgs  Vt  ds Vds
V  = mCox
 2 L

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 12

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current


I ds   Vgs  Vt 
Vdsat V
 dsat
 2 

  Vt 
2
 V gs
2

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 13

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 14

 Example
 We will be using a 0.6 mm process for your project
– From AMI Semiconductor
– tox = 100 Å 2.5
V =5
– m = 350 cm /V*s
gs
2
2
– Vt = 0.7 V 1.5 V =4

Ids (mA)
gs

 Plot Ids vs. Vds 1

– Vgs = 0, 1, 2, 3, 4, 5 0.5
V =3 gs

– Use W/L = 4/2 l

V =2 gs
V =1 gs
0
0 1 2 3 4 5
W  3.9  8.85 1014   W  W Vds
  mCox   350   8    120 μA/V2
L  100 10  L  L

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 15

 pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
0

 Thus pMOS must be wider to

Vgs = -1
Vgs = -2

-0.2
provide same current Vgs = -3

– In this class, assume

Ids (mA)
-0.4
Vgs = -4

mn / mp = 2 -0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 16

 Assignment
 Consider an nMOS transistor in a 0.6 mm process
with W/L = 4/2 l (i.e., 1.2/0.6 mm). In this process,
the gate oxide thickness is 100 Ao and the mobility of
electrons is 350 cm2/V· s. The threshold voltage is
0.7 V. Plot Ids vs. Vds for Vgs = 0, 1, 2, 3, 4, and 5 V.

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 17

 3. C-V Characteristics
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 18

 Gate Capacitance
 Approximate channel as connected to source
 Cg = CoxWL = CpermicronW
 Cpermicron = CoxL = eoxL/tox
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 19

 Gate Capacitance
 When the transistor is off, the channel is not inverted
Cg = Cgb = eoxWL/tox = CoxWL
 Let’s call CoxWL = C0
 When the transistor is on, the channel extends from the source
to the drain (if the transistor is unsaturated, or to the pinchoff
point otherwise)
Cg = Cgb + Cgs + Cgd

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 20

 Gate Capacitance

In reality the gate overlaps source and drain.

Thus, the gate capacitance should include not
only the intrinsic capacitance but also parasitic
overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 21

Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 22

 Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 23

Lumped representation of the MOSFET capacitances

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 24

 Review
1. Which factors affect to switching speed of MOS
transistors?
2. What are three operation modes of MOS
transistors?
3. When is a MOS transistor OFF?
4. When does a MOS transistor operate in saturation
region?
5. What does the drain-source current Ids depend on?
6. What does the gate capacitance Cg depend on?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 25

4. DC Transfer Characteristics
 Assuming the input changes slowly enough that
capacitances have plenty of time to charge or
discharge.
 Specific ranges of input and output voltages are
defined as valid 0 and 1 logic levels

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 26

 DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 27

 Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 28

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 29

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 30

 I-V Characteristics
 Make pMOS is wider than nMOS such that n = p
Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 31

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 32

 Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 33

 Load Line Analysis
 Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
dsn, |Idsp
Idsn dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 34

 DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 35

 Operating Regions
 Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 36

 Beta Ratio
 If p / n  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
p
 10
n
Vout 2
1
0.5
p
 0.1
n

0
VDD
Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 37

 Noise Margins
 How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 38

 Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

 p/ n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 39

 Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 40

 Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD Vout(t)
Cload
dVout (t ) I dsn (t )
 Idsn(t)
dt Cload
Vin(t)

 0 t  t0

I dsn (t )   
   Vout  VDD  Vt
2
2 V DD V Vout(t)
 t
  VDD  Vt  out 2  V (t ) V  V  V
V (t )
 out t0
  
out DD t

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 41

 Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 42

 Pass Transistor Ckts

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 43

 Pass Transistor Ckts

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 44

 Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

CMOS VLSI Design 4th Ed.

Transmission gate ON resistance

CMOS VLSI Design 4th Ed.

 Review
1. What are conditions for Vgs when the nMOS is in cutoff, linear,
and saturated modes?
2. What is noise margin?
3. What is transmission gate and its applications?
4. What are Vtp and Vtn ?
5. Give expressions for the output voltage.

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 47