Topic 2-Ic Fabrication Process

DEE6113 – CMOS INTEGRATED
CIRCUIT DESIGN
INTEGRATED CIRCUIT
FABRICATION PROCESS
2.1 How Single crystal silicon is formed
2.2 Basic process steps for wafer preparation
2.3 IC basic fabrication process
2.4 Fabrication process for CMOS IC
2.5 Concept of MEMs
2.6 MEMs fabrication process

CRYSTAL GROWTH
TYPES OF SILICON CRYSTAL STRUCTURE
 Solid materials exist in the form of crystal and

amorphous.
 For solid crystal, atoms that form the solid are

arranged periodically.
 If all the atoms are arranged periodically all over the

solid, the material is defined as single crystal.
 If the atoms arranged in a few different single crystal

structure, the solid is defined as polycrystal.
CRYSTAL GROWTH
1. Single Crystal
 Atoms are arranged uniformly all over the material.
Single crystal structure

CRYSTAL GROWTH
SINGLE CRYSTAL
 Integrated circuits are built on single-crystal silicon substrates

that possess a high level of purity and perfection.
 Single-crystal silicon is used in VLSI fabrication since this

structure does not have defects. Such defects have been known
to limit the lifetimes of minority carriers.
 Aside from the need to be single-crystalline in nature, silicon

substrates must also have a high degree of chemical purity, a
high degree of crystalline perfection, and high structure
uniformity.
CRYSTAL GROWTH
2. Polycrystalline silicon
 Polycrystalline silicon (or polysilicon) is a material consisting of
multiple small silicon crystals.
Polycrystalline Structure
CRYSTAL GROWTH
POLYCRYSTAL
 At the component level, polysilicon is used

as the conducting gate material in MOSFET
and CMOS processing technologies.
CRYSTAL GROWTH
3. Amorphous
 an amorphous or non-crystalline solid that
lacks the long-range order characteristic of a
crystal.
Amorphous Silicon Structure

CRYSTAL GROWTH
AMORPHOUS
Amorphous silicon has become the

material of choice for the active layer in
thin-film transistors (TFTs), which are most
widely used in large-area electronics
applications, mainly for liquid-crystal
displays (LCDs).
CRYSTAL GROWTH
Crystalline Structure For
IC Fabrication
Distillation & Reduction Crystal growth
Penyulingan & penurunan
Single
Raw material Polycrystalline
crystal
Polysilicon Rod Preparation
RAW MATERIAL Wafer is produced from raw material, that is silicon
(SAND/SILICON DIOXIDE)
that is obtained from 99.99% pure sand heated in
high temperature.
SILICON DECOMPOSITION Sand and carbon is heated together to

SiO2 + C Si + CO2
decompose silicon from silicon dioxide.
SILICON REFINEMENT Silicon is heated with hidrochloric acid at 1000˚C to

Si + 3HCL SiHCL3 + H2 produce silicon trichlorosilane and hydrogen gas is
released. This process is done to refine silicon.
ULTRA-PURE POLYSILICON ROD FORMATION

Silicon trichlorosilane is heated with
SiHCL3 + H2 Si + 3HCL hydrogen at 1000˚C to get the ultra-pure
silicon with 99.99999% pure.
Single Crystal Growth
 Crystalline Growth process is carried out to
change the structure of a polycrystalline to
single crystal.
 2 methods:
 Czochralski Method (CZ ) (cho-HRAL-skee )
 Float Zone Method (FZ)
Polycrystalline Single crystal
Crystal growth
Wafer Preparation
WHY USE SILICON!!!
☻Silicon is widely used in semiconductors because

it remains a semiconductor at higher
temperatures than the semiconductor germanium.
☺A pure state of it is easily grown in a furnace relau

and forms a better semiconductor/dielectric
interface than any other material.
WAFER PREPARATION
CZOCHRALSKI METHOD
Gas inlet Clock-wise

rotation
Crystal seed
Single crystal
Quartz crucible
Melted Polycrystalline silicon + r.f. coil

dopants (Boron/Phosporus)
Gas outlet
Counter
clock-wise
rotation
CRYSTALLINE GROWTH : CZOCHRALSKI
Seed down Seed pulling shouldering Growth& withdrawal
Czochralski
WAFER PREPARATION
CZOCHRALSKI PROCESS
1. The polycrystalline silicon is melted in a quartz crucible nearly
above the melting point of silicon. Dopants (e.g. boron or
phosphorus) can be added to the melt to achieve appropriate
electrical characteristics of the single crystal .
2. A seed crystal (a perfect single crystal) on a rotating rod is
brought to the surface of the silicon melt.
3. In contact with the seed crystal, the melt overtakes its crystal
structure.
4. The seed is slowly pulled upward with constant rotation, while
there is constant contact with the melt.
5. The crucible turns in the opposite direction of the seed crystal.
6. A constant temperature of the melt is essential to ensure a
steady growth.
Single Crystal Growth: Czochralski
A puller rod with seed crystal for

growing single-crystal silicon
Crucibles used in
Czochralski method
WAFER PREPARATION
CZOCHRALSKI METHOD
CZOCHRALSKI METHOD
Important term
WAFER PREPARATION
WAFER
A wafer is a thin slice of

semiconductor material such as
a silicon crystal, used in the
fabrication of integrated circuits
and other micro-devices.
The wafer serves as the

substrate for microelectronic
devices.
Electronics use wafer sizes from

100mm (6 inch) - 300mm (12 inch)
diameter.
WAFER PREPARATION
CZOCHRALSKI METHOD
INGOT CHARACTERISTICS:
 The diameter of the single crystal is

determined by the drawing speed,
which provides 2 to 25 cm/h. The
higher the drawing speed, the thinner
the crystal.
 Ingot diameter is between 100-
200mm.
 Ingot with the diameter of 100mm can
be grown up to 140cm long.
 The material resistivity, ρ is between
0.01 to 50 Ω - cm.
WAFER PREPARATION
FLOATING ZONE METHOD
Clock-wise
Gas inlet rotation
Crystal seed
Single crystal
r.f coil moving

downward
Polycrystalline
silicon
Gas outlet
Counter clock-
wise rotation
Single Crystal Growth: Float zone
WAFER PREPARATION
1. A seed crystal, which is introduced to the end of the

polycrystalline silicon rod, sets the crystal structure.
2. The heated region is slowly guided along the rod, the
polycrystalline silicon rod slowly transforms into a single
crystal.
3. Since only a small portion of the polycrystalline silicon is
molten, it can hardly be polluted (impurities accumulate at the
bottom since their higher solubility).
4. The doping is done by additions of dopants into the inert gas
(e.g with diborane or phosphine) which flows around the
apparatus.
WAFER PREPARATION
WAFER PREPARATION
INGOT CHARACTERISTICS:
 Diameter is usually between 50-150 mm
 Ingot with the diameter of 110 mm can be
grown up to 110cm long.
 The material resistivity, ρ is between 10 to
200 Ω - cm which is very suitable for
power devices and sensors.
Overview
WAFER PREPARATION
WAFER FORMATION PROCESS
SINGLE CRYSTAL GROWTH
(CZ OR FZ) - INGOT IS GROUNDED TO GET UNIFORM DIAMETER
INGOT DIAMETER
GRINDING - FLATS CUT INTO ONE OR MORE SIDES INDICATING THE
CRYSTALLOGRAPHIC PLANES OF THE WAFER
- FLATS AT DIFFERENT ANGLES ADDITIONALLY CONVEYED THE DOPING
FLATS AND NOTCHES TYPE
SHAPED ALONG THE INGOT - A SINGLE SMALL NOTCH IS TO CONVEY THE WAFER ORIENTATION
WAFER SLICING THE INGOT IS SLICED WITH A DIAMOND SAW TO FORM

WAFERS.
WAFER SURFACE POLISHING
WAFER IS READY FOR IC

PROCESSING
PREPARING WAFER
- To get uniform diameter

Crystal growth
CZ or FZ -Grind to shape the wafer edge
-Etching is done to smooth the surface
Diameter grinding
Preparing crystal ingot for grinding

Flat/ notch
Slicing
Polish
Diameter grind
Wafer is ready for fabrication

PREPARING WAFER
Flat/ notch: For orientation purpose

- Allow consistent alignment
Crystal growth
CZ or FZ
Diameter grinding
Flat/ notch Preparing crystal ingot for

grinding
Slicing
Diameter
Polish grind
Flat grind
PREPARING WAFER
Ingot is sliced using diamond saw

Crystal growth
CZ or FZ
Diameter grinding
Flat/ notch
Slicing
Polish

PREPARING WAFER
Crystal growth
CZ or FZ
Diameter grinding
Flat/ notch
Slicing Polishing the wafer to smoothes the

uneven surface and makes the wafer
flat and smooth enough to support
Polish
optical photolithography.

PREPARING WAFER
Crystal growth
CZ or FZ
Diameter grinding • Wafer is cleaned and ready for ic

fabrication process
Flat/ notch
Slicing
Polish

WAFER PREPARATION
WAFER SLICING & POLISHING
SILICON WAFER
epitaxial
 Define epitaxial layer.

 State the reason why epitaxial layer is important for
wafers.
 three methods of epitaxial growth techniques:
 Vapour Phase Epitaxy (VPE) (wap)
 Molecular Beam Epitaxy (MBE) (sinaran molekul)
 Metal Organic Chemical Vapour
Deposition (MOCVD) with the aid

(wap metal organic)
of suitable diagram.
Why Epitaxy?
 To enhance the performance of discrete bipolar
transistor.
 To improve the performance of dynamic
random access memory devices (RAMs).
CHARACTERISTIC OF WAFER
READY TO FOR IC
FABRICATION
Trend of producing large wafer
Trend of producing large wafer
OXIDATION
Oxidation is a chemical process

whereby the silicon reacts with
oxygen to produce oxide layer,
known as silicon dioxide (SiO2).
OXIDATION
FUNCTIONS OF OXIDE LAYER
1. To protect the wafer surface physically from damages.

2. To protect wafer from dust or impurities.
3. To protect wafer from chemical reactions due to
contamination.
4. Act as insulator during doping process.
5. Act as dielectric on the wafer surface to prevent short
circuit between metal layers.
6. Act as gate terminal dielectric in MOS transistor.
OXIDATION
TYPES OF OXIDE LAYER
 Types of oxide layer:

i. Thick oxide layer (Field Oxide)
ii. Thin oxide layer (Gate Oxide)
OXIDATION
Field Oxide
 Field Oxide is used to isolate transistors.

OXIDATION
Thin Oxide
 Thin Oxide is used to form thin layer of gate oxide in MOS transistor
OXIDATION
2 TYPES OF OXIDATION PROCESS
1.Wet oxidation process

2. Dry oxidation process
OXIDATION
WET OXIDATION PROCESS
Water vapor
O2
Wet oxidation
• Wet oxidation is carried out through the
combination of wet vapor with silicon to
produce silicon oxide.
• Oxygen gas is flowed to the container with
water & heated to the boiling point
• Chemical reactions involved during the
reaction of silicon with water vapor:
Si + 2H2O SiO2 + 2H2
• As a result an insulating layer of SiO2 is
formed on the surface of silicon wafers.
Wet oxidation
 Fast growth rate
 Fast growth even on low temperatures
 Result in thick oxide but lower quality
OXIDATION
DRY OXIDATION PROCESS
Dry oxidation
 Pieces of silicon wafers are prepared in a quartz
tube.
 Dry oxygen gas flow to the quartz tube and the
wafer is then heated to 1100 ˚ c in the presence
of dry oxygen gas.
 Dry oxygen gas is absorbed slowly over the
pieces of wafer through chemical reactions
follows:
Si + O2  SiO2
 As a result an insulating layer of SiO2 is formed
on the surface of silicon wafers.
Dry oxidation
 Advantages
 Good quality
 Lower growth rate
 results in a higher density oxide
 Oxide layer is thin but durable
Wet Vs Dry Oxidation
Wet Oxidation Dry Oxidation
Reaction time Higher growth rate Lower growth rate
Reaction 900ºC 100nm/h 19nm/h
temperature
1000ºC 400nm/h 50nm/h
1100ºC 630nm/h 120nm/h
Layer thickness thick Thin – 100nm
thickness
Layer quality Low quality High quality

DOPING
DOPING
Phosphorus and arsenic is used to produce n-type doped silicon.

DOPING
Boron, gallium or indium is used to produce p-type doped silicon.

DOPING
 Functions of doped layer:

 To control the silicon resistance
 To conduct more current flow through n-type or p-
type carriers available.
 3 methods of doping process:

 Diffusion
 Ion implantation
 Epitaxy
DOPING
DIFFUSION
DOPING
DIFFUSION
DOPING
DIFFUSION
 Predeposition
• Dopant source is supplied.
• Wafer is heated between 1000°C to 1200°C.
• Dopant is deposited by controlling time and
temperature in the specified amount of dopant.
• Impurities is deposited on the wafer surface until the
solid solubility level is achieved.
DOPING
DIFFUSION
 Drive in
• No more dopant is supplied.
• Drive in is done to drive the dopants on the wafer
surface into the substrate according to the specified
depth by controlling temperature and time.
• Variable such as time, temperature and ambient gas is
controlled to obtain the specified junction depth.
DOPING
ION IMPLANTATION
 A method of depositing/implanting dopants into

the crystal lattice by accelerating the controlled
density of dopant ions and the process is done
in room temperature.
 This method can produce a thin layer with high

density dopant.
 2 parameters that can be precisely controlled

are:
• Junction depth.
• Dopant density.
DOPING
ION IMPLANTATION
DOPING
ION IMPLANTATION
 Ion implantation method is used widely in large scale IC

fabrication.
 Dopant ion beam (boron @ phosphorus) is accelerated

with high energy(10-1000V).
 Ion implantation causes crystalline damage which must be

annealed.
DOPING
ION IMPLANTATION EQUIPMENT
DOPING
DOPING
DOPING
ION IMPLANTATION
5. FOTOLITOGRAFI
TAKRIF
 Fotolitografi adalah teknik yang digunakan untuk
membuat corak tertentu pada permukaan wafer.
 Corak yang dibentuk adalah bergantung struktur

mikro yang hendak difabrikasikan seperti peranti
elektronik dan litar bersepadu.
 Tujuan proses ini adalah untuk membentuk bukaan-

bukaan untuk proses-proses resapan, implantasi ion
dan pelogaman.
5. FOTOLITOGRAFI
PHOTOLITOGRAPHY
PHOTO MASK
Opaque zone
Transparent zone
 Photo mask is a piece of glass have opaque pattern and

transparent pattern on its surface
 Opaque pattern act as prevent UV radiance from penetrate
photo mask
 Transparent pattern allow UV's radiance penetrate photo mask
PHOTOLITOGRAPHY
PHOTO MASK
Opaque zone
Transparent zone
 Size and position form the pattern of photomask is very precise
 Process of transferring the pattern from photomask to wafer is known

as s photolithography proces
PHOTO MASK
Example of IC photo mask

PHOTOLITOGRAPHY
PHOTO RESIST LAYER
 There were 2 type photoresist:-
 Positive photoresist( + ve )
 Negative photoresist( - ve )
 Photo resist criteria :-

 It must be stick perfectly on the surface
substratum
 Thickness of photoresist must be uniform
5. FOTOLITOGRAFI
RINTANG FOTO POSITIF
Menyebabkan kawasan terdedah terbuang
bila dipunarkan
5. FOTOLITOGRAFI
RINTANG FOTO NEGATIF
Kawasan yang terdedah kepada cahaya UV tidak
terbuang apabila dipunarkan.
5. FOTOLITOGRAFI
SEQUENCE OF
PHOTOLITHOGRAPHY PROCESS
Wafer cleaning
Coat with photoresist
Pre -bake to semi-harden the photoresist
With photo mask then are exposed to UV

light
SEQUENCE OF
PHOTOLITHOGRAPHY PROCESS
Remove the photomask.
The unexposed part of photoresist is
etched away
Post-Bake in high temperature to harden
the remaining photoresist
Etching: the SiO2 layer that uncovered

by polymer layer is etched away
Etching: the photoresist is etched away

METALIZATION
DEFINITION
 Metallization is a process to generate
interconnection among components on chip
 It is established through the process

deposition a thin layer of Aluminium metal on
wafer surface.
METALIZATION
Metallization
 There are four common structure in
metallization: interconnects, contacts, vias,
plugs and interconnects.
Metal 3
Metal 2
Metal 1
Silicon
METALIZATION
Metallization
 Interconnect: Metal layer. The IC has more
than one layer of interconnects, each layer
has different name, starting with the first layer
deposited, “Metal 1”, “Metal 2”, etc.
 Virtually all IC circuits are made with 2-6
levels
of metal wiring
METALIZATION
Metallization
IBMs 7 layer Copper Metallization Technology (1998)

METALIZATION
Metallization
 Contact: A hole in the Si dioxide layer that
connect the transistors to the first metal layer.
 Via: A hole in the Si dioxide layer that
connect two metal layers.
 Plug: A metal layer that fills either a contact
or a via. Made of either tungsten (W) or
aluminum (Al).
METALIZATION
Metallization
METALIZATION
METALIZATION MATERIAL
 Metal type that use for metal layer.
 Aluminium
 Titanium
 Platinum
 Gold
 Molibdenum
 Tantalum
 Non-metal for metalization function
 Polisilikon – MOS Gate transistor area
 Copper and Aluminium always use in devices
connection.
METALIZATION
METALIZATION PROCESS
METALIZATION
METALIZATION
METALIZATION
6. PELOGAMAN/METALLIZATION
ETCHING
DEFINITION
 Etch
 Definite as material removal
 Carve(mengukir) on metal by using acid
 Etching
 Etching is a process in which material is removed from
selected regions of the substrate.
 Remove layer materials as silicon oxide ( SiO2 ),
silicon nitric (Si3N4) and polysilicon that are not
required in a particular place on wafer surface.
 Etching Process
 In forming components of wafer, these materials only
required in certain area only
 Each etching process only remove one types of material
only
ETCHING
OBJECTIVES
 To remove photo resist and oxide layer on
the wafer surface in the photolithography
process
 To remove surface damages during cutting

wafer to remove jagged effects around
wafer.
 Remove metal layer which are not required

in metallization
ETCHING
ETCHER
ETCHANT ETCHED LAYER
HYDROFLUORIC ACID (HF) / NITRIC ACID SiO2
HYDROFLUORIC ACID (HF) SILICON NITRIDE
PHOSPHORIC ACID/ NITRIC / ASETIC ALUMINIUM
NITRIC ACID + HYDROFLUORIC ACID (HF) POLYSILICON
SULFURIC ACID + ASETON + TRIKLOROETERINA PHOTO RESIST
Keperluan Proses Punaran

Saiz pertumbuhan wafer = 400 mm
Saiz kesusutan bahagian muka kurang daripada 0.5 um
ETCHING
WET DRY
ETCHING ETCHING
ETCHING
WET ETCHING
• Use liquid chemicals

• highly selective with respect to mask and substrate
• used in the manufacturing of circuits with feature sizes
larger than 3 microns.
• isotropic- etches in all directions at the same rate
Resist
SiO2
Substrate
ETCHING
WET ETCHING
 Known as under cutting ( happen to targeted

material and its edges)
Undercut
Resist
Overetch Film
Substrate
ETCHING
WET ETCHING
Wafers are immersed in a tank of Operator shown placing a cassette of

liquid reactants wafers into an acid bath
Example of wet etching

ETCHING
DRY ETCHING
 React with chemically reactive gases/ plasma
 Used to define circuit features smaller than 3 microns
 greater control over the process parameters
(e.g. pressure, temperature, gas flow, power).
 Can be isotropy & anisotropy (etch in one direction)
- controllable
Resist
SiO2
Substrate
ETCHING
DRY ETCHING
Example of dry etching

ETCHING
ETCHING
 3 situation after the Etching Process
Normal
Over etch
Resist Lifting
COMPARISION BETWEEN
WET AND DRY ETCHING
WET ETCHING DRY ETCHING
METHOD Chemical solutions Plasma / ion bombardment
ADVANTAGE 1. Low cost, easy to 1. Capable of defining
implement small feature size
2. High etching rate
3. Good selectivity for most
materials
DISADVANTAGE 1. Inadequate for defining 1. High cost, hard to
feature size < 1um implement
2. Potential of chemical 2. Low throughput
handling hazards 3. Poor selectivity
3. Wafer contamination 4. Potential radiation
issues damage
DIRECTIONALITY Isotropic Anisotropic
7. PUNARAN/ETCHING
PROFIL PUNARAN
7. PUNARAN/ETCHING
PROFIL PUNARAN
MOS TRANSISTOR FABRICATION
• MOS transistor is known as MOSFET (metal

oxide semiconductor field-effect transistor).
• MOSFET that is widely used in integrated

circuit is the CMOS technology (combination
of NMOS and PMOS).
• MOSFET is widely used nowadays in

electronic equipment, e.g. mobile phone,
computer, medical electronic equipment, etc.
111
NMOS Fabrication Sequence Process
 Step 1
Substratum P
Processing is carried out on a thin wafer cut from single

crystal of silicon high purity into which the required p-
impurities are introduced as the crystal is grown.
 Step 2
Thick Oxide (1µm)
Substratum P
A layer of silicon dioxide (SiO2) is grown all over the

wafer to protect the surface, act as a barrier to dopants
during processing, and provide insulating substrate onto
others layers may be deposited and patterned.
 Step 3
Photoresist
Thick Oxide (1µm)
Substratum P
The surface is now covered with a photoresist which is

deposited onto the wafer and spun to achieve an even
distribution of the required thickness
 Step 4
Photomask
Photoresist
Thick Oxide (1µm)
Substratum P
The photoresist layer then exposed to UV light through a

mask which defines those regions into which diffusion is
to take place together with transistor channels.
 Step 5
Photoresist Window in oxide
Substratum P
These arcas are etched away together with the

underlying silicon dioxide so that the wafer surface is
exposed in the window defined the mask..
 Step 6 Pattern poly on

thin oxide
Substratum P
The remaining photoresist is removed and a thin layer of

SiO2 (0.1um typical) is grown over the entire chip surface
and then polysilicon is deposited on top of this to form
the gate structure.
 Step 7
n+ n+
Substratum P
Further photoresist coating and masking (As shown in

step 6), and then the thin oxide is removed to expose
areas into which n-type impurities are to be diffused to
form the source and drain as shown.
 Step 8
n+ n+
Substratum P
Thick oxide (SiO2) is grown over all again and is then

masked with photoresist and etched to expose selected
areas of the polysilicon gate and the drain and sources
areas where connections are to be made.
 Step 9
n+ n+
Substratum P
The whole chip then has metal (aluminum) deposited

over its surface to a thickness typically of 1um. This
metal layer is then masked and etched to form the
required interconnection pattern
N-WELL
FABRICATION
PROCESS
N-WELL Fabrication Sequence Process
Thick Oxide
(1µm)
Substratum P
Grow SiO2 on top of Si wafer

Photoresist
Thick Oxide
(1µm)
Substratum P P
Substratum
Spin on photoresist
UV Light
Photomask
Substratum
SubstratumPP
• Expose photoresist through n-well mask

• Strip off exposed photoresist
Substratum P
Etch oxide with hydrofluoric acid (HF)

Substratum P
Strip off remaining photoresist

N-well
n-well is formed with diffusion or ion implantation

N-well
Strip off the remaining oxide using HF

Polysilicon
Thin gate oxide
N-well
• Deposit very thin layer of gate oxide

• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysiliconHeavily doped
to be good conductor
UV Light
Photomask
N-well
Use same lithography process to pattern polysilicon

N-well
Etch oxide the remaining polysilicon

N-well
• Use oxide and masking to expose where n+ dopants

should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
UV Light
Photomask
N-well
• Pattern oxide and form n+ regions

• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ n+ n+
N-well
Historically dopants were diffused

n+ n+ n+
N-well
Strip off oxide to complete patterning step

n+ n+ n+
N-well
p+ n+ n+ p+ p+ n+
N-well
Similar set of steps form p+ diffusion regions for pMOS source

and drain and substrate contact
p+ n+ n+ p+ p+ n+
N-well
• Now we need to wire together the devices

• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
p+ n+ n+ p+ p+ n+
N-well
p+ n+ n+ p+ p+ n+
N-well
• Sputter on aluminum over whole wafer

• Pattern to remove excess metal, leaving wires
 Number of mask needed:
 Six masks
 n-well
 Polysilicon
 n+ diffusion
 p+ diffusion
 Contact
 Metal
P-WELL Physical Structure
p+ p+ n+ n+
p+
Substratum-n
PROBLEMS IN CMOS OPERATION – LATCH UP
 Latchup is a term used in integrated circuits

(ICs) to describe a particular type of short circuit
which can occur in an improperly designed
circuit.
 More specifically it is the inadvertent creation of
a low-impedance path between CMOS ICs
between the power supply and the ground rails
due to interaction of parasitic pnp and npn
bipolar transistors.
 The origin - Position of the two transistors n and

p that are close in CMOS technology can be a
problem for device operation.
 The parasitic structure is usually equivalent to a

thyristor (or SCR), a PNPN structure which acts
as a PNP and an NPN transistor stacked next to
each other.
Note
• Structure on the physical and electronic

level, and the thyristor / SCR symbol.
 During a latchup when one of the

transistors is conducting, the other
one begins conducting too. They
both keep each other in saturation
for as long as the structure is
forward-biased and some current
flows through it - which usually
means until a power-down.
 Effect Of Latch-Up:
 This causes excessive current flows and potential
permanent damage to the devices.
 It will cause a short circuit between Vdd to Vss
 Solution :
 The gain of the transistor and resistor made small
PROBLEMS IN CMOS OPERATION – Parasitic capacitance
 Every time a transistor is turned on, it must first

charge all of its internal (parasitic) capacitance
before it can begin to conduct.
 The time it takes to charge up and discharge
(turn off) the parasitic capacitance is much
longer than the actual turn on and off of the
transistor.
 If the parasitic capacitance can be reduced, the
transistor can be switched faster —
performance.
 The Origin - One of the major source of
parasitic capacitance is from the source and
drain to substrate junctions.
 SOI can reduced the capacitance at the
source and drain junctions significantly — by
eliminating the depletion regions extending
into the substrate.
 Effect Of Parasitic Capacitance

 It will cause unwanted switching
 Solution
 Using the method of ‘self row’ in which the source
and drain both does not diffuse into the area
under the gate simultaneously.
 Using Silicon On Insulator (SOI) technology
WHAT IS MEMS??
 Micro-Electro-Mechanical Systems (MEMS) is the

integration of mechanical elements, sensors,
actuators, and electronics on a common silicon
substrate through microfabrication technology
PLAY
More on “What are MEMS?”
• MEMS devices first took off in the sensor

industry.
• Most MEMS devices have at least one
transducer element.
– To sense
– To actuate
• Transducer is a device or system that converts
one form of energy to another – force to voltage,
voltage to force, …
How Does It Work????
• Components:
􀂃 Microelectronic Integrated Circuits (the brains of the
system)
• It receives and processes data, and makes decisions.
The data received comes from the micro-sensors in the
MEMS.
􀂃 Micro-Sensors (the eyes and arms)
• They constantly gather data from the surrounding
environment and pass this information on to the
microelectronics for processing
􀂃 Micro-Actuator (the decision-maker)
• Acts as a switch or a trigger to activate an external
device. If this decision is reached, the microelectronics
will tell the micro actuator to activate this device
Examples of MEMS
More on MEMS Applications
MICROELECTRONICS VS MEMS
• One way to look at it:

– IC’s move and sense electrons
– MEMS move and sense mass
• Another:
– IC’s use Semiconductor processing technologies
– MEMS can use a variety of processes including Semiconductor
but also Bulk, LIGA, Surface Micromachining…
• Packaging
– IC packaging consists of electrical connections in and out of a
sealed environment
– MEMS packaging not only includes input and output of electrical
signals, but may also include optical connections, fluidic
capillaries, gas channels and openings to the environment. A
much greater challenge.
Advantages Of MEMS
Cost
Because of the increase in micromachining Reliability
technology, hundreds of MEMS can be made from a MEMS have no moving parts, so they are
single 8-inch wafer of silicon. Therefore, the cost for much more reliable than a macro system
a MEMS is very low.
Limitless
Size Because of the reduced cost and increased
Since an entire system can be made this small and reliability, there is almost no limit to what MEMS can
in such quantities, prices are reduced for products be used for
which incorporate this technology. In addition, its
size makes it very easy to incorporate into almost
any environmental
MEMS Applications
 MEMS application can be divided

into MEMS based on
actuator
sensor.
MEMS Fabrication Process
• There are THREE MEMS fabrication process:

– Bulk Micromachining
– Surface Micromachining
– LIGA (lithography, electroplating and molding)
What Is Micromachining???
Micromachining is the process of making really
small parts. These components could be anything
from a diode to a toothed gear that is the size of a
pen tip.
Bulk Micromachining
• Bulk micromachining is a method of making
extremely tiny mechanical or electrical
components.
• This process typically uses wafers of silicon, but
will occasionally use plastic or ceramic material as
well. Bulk micromachining starts with a solid piece
and removes material until it reaches its final
shape.
Bulk Micromachining
• Bulk micromachining defines structures by

selectively etching inside a substrate
• Bulk micromachining starts with a silicon wafer
or other substrates which is selectively etched,
using photolithography to transfer a pattern from
a mask to the surface.
• bulk micromachining can be performed with wet
or dry etches, although the most common etch in
silicon is the anisotropic wet etch.
Bulk Micromachining
• Example : Silicon cantilever beam

Surface Micromachining
• surface micromachining builds microstructures

by deposition and etching of different structural
layers on top of the substrate. The bulk of the
substrate remains untouched.
• Generally polysilicon is commonly used as one
of the layers and silicon dioxide is used as a
sacrificial layer which is removed or etched out
to create the necessary void in the thickness
direction
• The surface micromachined components are
smaller compared to the bulk micromachining.
• Micromachining starts with a silicon wafer or

other substrate and grows layers on top. These
layers are selectively etched by photolithography
and either a wet etch involving an acid or a dry
etch involving an ionized gas, or plasma.
• Surface micromachining can involve as many
layers as is needed with a different mask
(producing a different pattern) on each layer
• Complicated components, such as movable parts, are

built using a sacrificial layer. For example, a suspended
cantilever can be built by depositing and structuring a
sacrificial layer, which is then selectively removed at the
locations where the future beams must be attached to
the substrate (i.e. the anchor points).
• The structural layer is then deposited on top of the
polymer and structured to define the beams. Finally, the
sacrificial layer is removed to release the beams, using a
selective etch process that will not damage the structural
layer.
Basic depiction of (a) bulk and (b) surface micromachining

LIGA
• LIGA is a German acronym for Lithographie,
Galvanoformung, Abformung (Lithography,
Electroplating, and Molding) that describes a
fabrication technology used to create high-
aspect-ratio microstructures.
• LIGA processes combine IC lithography and
electroplating and molding to obtain depth.
Patterns are created in a substrate and then
electroplated to create 3D molds. These molds
can be used as the final product, or various
materials can be injected into them
LIGA
LIGA
• The LIGA consists of three main processing
steps; lithography, electroplating and molding
• There are two main LIGA-fabrication
technologies, X-Ray LIGA to create high-aspect
ratio structures, and UV LIGA, a more
accessible method which uses ultraviolet light to
create structures with relatively low aspect ratios
• Electroforming is a process for creating 3-
dimensional metal parts by using a carefully
controlled long-duration electroplating process
LIGA

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DEE6113 – CMOS INTEGRATED

2.2 Basic process steps for wafer preparation

2.3 IC basic fabrication process

2.4 Fabrication process for CMOS IC

2.5 Concept of MEMs

2.6 MEMs fabrication process

 Solid materials exist in the form of crystal and

 For solid crystal, atoms that form the solid are

 If all the atoms are arranged periodically all over the

 If the atoms arranged in a few different single crystal

Single crystal structure

 Integrated circuits are built on single-crystal silicon substrates

 Single-crystal silicon is used in VLSI fabrication since this

 Aside from the need to be single-crystalline in nature, silicon

 At the component level, polysilicon is used

Amorphous Silicon Structure

Amorphous silicon has become the

SILICON DECOMPOSITION Sand and carbon is heated together to

SILICON REFINEMENT Silicon is heated with hidrochloric acid at 1000˚C to

ULTRA-PURE POLYSILICON ROD FORMATION

WHY USE SILICON!!!

☻Silicon is widely used in semiconductors because

☺A pure state of it is easily grown in a furnace relau

Gas inlet Clock-wise

Melted Polycrystalline silicon + r.f. coil

Seed down Seed pulling shouldering Growth& withdrawal

A puller rod with seed crystal for

A wafer is a thin slice of

The wafer serves as the

Electronics use wafer sizes from

 The diameter of the single crystal is

r.f coil moving

1. A seed crystal, which is introduced to the end of the

WAFER SLICING THE INGOT IS SLICED WITH A DIAMOND SAW TO FORM

WAFER SURFACE POLISHING

WAFER IS READY FOR IC

- To get uniform diameter

Preparing crystal ingot for grinding

Wafer is ready for fabrication

Flat/ notch: For orientation purpose

Flat/ notch Preparing crystal ingot for

Ingot is sliced using diamond saw

Wafer is ready for fabrication

Slicing Polishing the wafer to smoothes the

Wafer is ready for fabrication

Diameter grinding • Wafer is cleaned and ready for ic

Wafer is ready for fabrication

 Define epitaxial layer.

 Molecular Beam Epitaxy (MBE) (sinaran molekul)

 Metal Organic Chemical Vapour

Deposition (MOCVD) with the aid

Oxidation is a chemical process

1. To protect the wafer surface physically from damages.

 Types of oxide layer:

 Field Oxide is used to isolate transistors.

1.Wet oxidation process

Layer quality Low quality High quality

Phosphorus and arsenic is used to produce n-type doped silicon.

Boron, gallium or indium is used to produce p-type doped silicon.

 Functions of doped layer:

 3 methods of doping process:

 A method of depositing/implanting dopants into

 This method can produce a thin layer with high