ARM

Advanced RISC Machines

Introduction and Architecture

 ARM Applications

Apple iPod Nano Ford Sync In-Car Comm &

Entertainment System

Nokia N93 Sony Playstation 3 (60GB)

 ARM Connected Community – 900+

Connect, Collaborate, Create – accelerating innovation

ARM Advantage
 Why ARM here ???

• ARM is one of the most licensed and thus

widespread processor cores in the world

• Used especially in portable devices due to low power

consumption and reasonable performance

• Several interesting extensions available like Thumb

instruction set and Jazelle Java machine
 ARM History

• ARM – Acorn RISC Machine(1983–1985)

– Acorn Computers Limited, Cambridge, England

• ARM – Advanced RISC Machine 1990

– ARM Limited, 1990

– ARM has been licensed to many semiconductor

manufacturers
 ARM History

• Key component of many 32 – bit embedded systems

• Portable Consumer devices

• ARM1 prototype in 1985

• One of the ARM’s most successful cores is the

ARM7TDMI,provides high code density and low
power consumption
 Advanced RISC Machines

• ARM Core uses a ________ architecture

• ARM is Physical hardware design company.

• ARM licenses its cores out and other companies

make processors based on its cores
 RISC vs. CISC Architecture
RISC CISC
Fixed width instructions Variable length instructions
Few formats of instructions Several formats of
instructions
Load/Store Architecture Memory values can be used
as operands in instructions
Large Register bank Small Register Bank

Instructions are pipelinable Pipelining is Complex

 RISC
• Advantage(s)
– A Smaller Die Size

– A Shorter Development Time

– Higher Performance (Bit Tricky)

• Disadvantage
– Generally poor code density (Fixed Length Instruction)
 CISC vs. RISC

CISC RISC
Greater
Compiler Compiler
Complexity

Code Generation Code Generation

Greater
Processor Processor
Complexity
 Features used from RISC

• A Load/Store Architecture

• Fixed Length 32-bit Instructions

• 3- Address Instruction Formats

 Load Store Architecture

• Memory can be accessed only through two

dedicated instructions
– LDR ; move word from memory to register

– STR ; move word from register to memory

• All other instructions have to work on registers only.

 3 Address Instruction Format

f bits n bits n bits n bits

Function op 1 addr. op 2 addr. dest. addr.

Example

Add d, s1, s2 ; d =s1+s2

 ARM Design Policy

• Reduce power consumption

• High code density

• Price sensitive

• Reduce the area of the die taken up by the

embedded processor

• ARM Incorporated hardware debug technology

 Instruction set for Embedded Systems

• Variable cycle execution for certain instructions

• Inline barrel shifter leading to more complex

instructions

• Thumb 16 – bit instructions

• Conditional execution

• Enhanced Instructions
 Barrel Shifter
• The barrel shifter is a functional unit which
can be used in a number of different
circumstances.
ARM Processor Fundamentals
 Registers

• ARM has Load Store Architecture

• General Purpose Registers can hold data or address

• Total of 37 Registers, each of 32 bit

• There are 17 or 18 active Registers

– 16 data registers

– 2 status registers
 Registers – User Mode

• Registers R0 – R12 are General Purpose Registers

• R13 is used as Stack Pointer (sp)

• R14 is used as Link register (lr)

• R15 is used as Program Counter (pc)

• CPSR is Current Program Status Register

• SPSR is Saved Program Status Register

 CPSR
31 28 24 23 16 15 8 7 6 5 4 0

N Z C V J U n d e f i n e d I F T mode

 hold information about the most recently performed ALU operation

 set the processor operating mode

• Condition code flags

– N = Negative result from ALU • Interrupt Disable bits.
– Z = Zero result from ALU – I = 1: Disables the IRQ.
– C = ALU operation Carried out – F = 1: Disables the FIQ.
– V = ALU operation oVerflowed • T Bit
• J bit – Architecture xT only
– Architecture 5TEJ only – T = 0: Processor in ARM state
– J = 1: Processor in Jazelle state – T = 1: Processor in Thumb state
• Mode bits
– Specify the processor mode
 Processor Modes
• ARM has seven basic operating modes
– Each mode has access to its own stack space and a different subset of registers
– Some operations can only be carried out in a privileged mode

Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes

Entered when a high priority (fast) interrupt is

FIQ
raised

IRQ Entered when a normal priority interrupt is raised

Privileged
modes
Abort Used to handle memory access violations

Undef Used to handle undefined instructions

Privileged mode using the same registers as User

System
mode
Mode under which most Applications / OS tasks Unprivileged
User
run mode
 The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1
r2 ARM has 37 registers, all 32-bits long
r3
r4 A subset of these registers is accessible in
r5 each mode
r6 Note: System mode uses the User mode
r7 register set.
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Current mode Banked out registers

2 new modes: Monitor & Hypervisor

 Banked Registers
• Banked registers are available only when the processor is in a
particular mode

• Every processor mode except user mode can change mode by

writing to the mode bits of the cpsr

• Banked registers are a subset of the main 16 registers

• If we change processor mode, a banked register from the new

mode will replace an existing register

• Exceptions and Interrupts cause a mode change

 Processor Mode
Mode Abbr: Privileged Mode[4:0]

Abort abt yes 10111

Fast Interrupt Request fiq yes 10001
Interrupt Request irq yes 10010
Supervisor svc yes 10011
System sys yes 11111
Undefined und yes 11011
User usr no 10000

cpsr is not copied into the spsr when a mode change

is forced due to a program writing directly to the cpsr.
 Operation Modes

Mode Registers CPSR[4:0]

User User 10000
FIQ _fiq 10001
IRQ _irq 10010
Supervisor Mode _svc 10011
Abort _abt 10111
Undefined Instruction _und 11011
System User 11111
 Processor Modes
User Unprivileged mode for most applications to run

FIQ Fast Interrupt Routine

IRQ Interrupt Routines
Supervisor Entered on reset and when there is a exception

Abort Entered when data or instruction prefetch aborted

Undefined When an undefined instructions is executed

System Privileged user mode for operating system

 State and Instruction Sets

• There are three instruction sets

– ARM
– Thumb
– Jazelle

The Jazelle instruction set is a closed instruction set and is not

openly available.

To take advantage of Jazelle extra software has to be licensed

from both ARM Limited and Sun Microsystems.
 State and Instruction Sets
ARM Thumb
(cpsr T = 0) (cpsr T = 1)
Instruction Size 32 bit 16 bit

Core Instruction 58 30

Conditional Execution Most Only branch

instructions
Data Processing Instructions Access to barrel shifter and Separate barrel and
ALU ALU instructions
Program Status Register R/W in privileged mode No direct access
Register Usage 15 GPR + PC 8 GPR + 7 high registers
+ PC
 State and Instruction Sets

Jazelle
(cpsr T = 0, J = 1)
Instruction Size 8 bit

Core Instruction Over 60% of the java bytecodes are

implemented in hardware; the rest of the codes
are implemented in software
 Switching States

• ARM to Thumb
– Execute the BX instruction with state bit=1

• Thumb to ARM
– Execute the BX instruction with state bit=0

– An interrupt or exception occurs

 Interrupt Masks

• Are used to stop specific interrupt requests from

interrupting the processor
– IRQ

– FIQ

• The I bit masks IRQ when set to binary 1, and F bit

masks FIQ when set to binary 1
 Condition Flags

• Condition flags are updated by comparisons and the

result of ALU operations that specify the S
instruction suffix
– If SUBS results in a register value of zero, then the Z flag in
the CPSR is set
 ARM Exceptions

• ARM supports range of Interrupts, Traps, Supervisor

Calls, all grouped under general heading of

Exceptions
 Exceptions

• RESET – when power is applied, branches to initialization

code
• UNDEF – when the processor cannot decode an instruction
• SWI – when a SWI instruction is called
• PABT – attempts to fetch an instruction from an address
without the correct access permissions
• DABT –attempts to access data memory without the correct
access permissions
• IRQ – by external hardware
• FIQ – by external hardware requiring faster response time
 Exception Priorities

1. Reset (Highest Priority)

2. Data Abort

3. FIQ

4. IRQ

5. Prefetch Abort

6. SWI, Undefined
 Vector Addresses
Exception / Interrupt Shorthand Address

Reset RESET 0x00000000

Undefined Instruction UNDEF 0x00000004

Software Interrupt SWI 0x00000008

Prefetch Abort PABT 0x0000000C

Data Abort DABT 0x000000010

Reserved - 0x000000014
Interrupt Request IRQ 0x000000018
Fast Interrupt Request FIQ 0x00000001C
 Exception Handling
• When an exception occurs, the core…
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits
• Change to ARM state (if appropriate)
0x1C FIQ
• Change to exception mode
0x18 IRQ
• Disable interrupts (if appropriate)
– Stores the return address in LR_<mode> 0x14 (Reserved)
0x10 Data Abort
– Sets PC to vector address
0x0C Prefetch Abort
• To return, exception handler needs to… 0x08 Supervisor Call
– Restore CPSR from SPSR_<mode> 0x04 Undefined Instruction
– Restore PC from LR_<mode> 0x00 Reset
Vector Table
• Cores can enter ARM state or Thumb state when
taking an exception

• Note that v7-M and v6-M exception model is different

 Exception handling process
1. Save processor status
Main – Copies CPSR into SPSR_<mode>
Application
– Stores the return address in LR_<mode>
– Adjusts LR based on exception type
2. Change processor status for exception
– Mode field bits
– ARM or Thumb state
Exception – Interrupt disable bits (if appropriate)
handler – Sets PC to vector address
3. Execute exception handler
– <users code>
4. Return to main application
– Restore CPSR from SPSR_<mode>
– Restore PC from LR_<mode>
• 1 and 2 performed automatically by the core
• 3 and 4 responsibility of software
 Core Extensions
• Standard components placed next to the ARM core

• Improve performance, manage resources, provide

extra functionality

• Three hardware extensions

– Caches

– Memory Management

– Coprocessors
 Caches
• Cache is a block of fast memory placed between
main memory and the core

• Cache provides an overall increase in

performance

• ARM has two forms of cache

– Single unified cache for data and instruction

– Separate caches for data and instruction

 Memory Management

• MMU is a class of processor hardware

components for handling memory accesses
requested by the CPU.

• The functions of MMU’s are

– Translation of virtual address to physical address.

– Memory protection

– Cache control etc.

 Coprocessors
• Coprocessors can be attached to the ARM processor

• A separate chip, that performs lot of calculations for the

microprocessor, relieving the CPU some of its work and
thus enhancing overall speed of system.

• A secondary processor used to speed up operation by

taking over a specific part of main processors work.

• The ARM processor uses coprocessor 15 registers to

control cache, TCMs, and memory management
 ARM processor families

• ARM7, ARM9, ARM10 and ARM11

• 7, 9, 10, 11 indicate different core designs

ARM Processor Families
 Architecture Revisions
Revision Example core ISA enhancement
Implementation
ARMv1 ARM1 First ARM Processor
26 – bit addressing
ARMv2 ARM2 32 – bit multiplier
32 – bit coprocessor support
ARMv2a ARM3 On chip cache
Atomic swap instruction
ARMv3 ARM6 & ARM7DI 32 – bit addressing
Separate cpsr & spsr
New modes – UNDEF, ABORT
MMU support – virtual memory
ARMv3M ARM7M Signed & unsigned long multiply
ARMv4 StrongARM Load – store instruction
New Mode - System
 Architecture Revisions
Revision Example core ISA enhancement
Implementation
ARMv4T ARM7TDMI & ARM9T Thumb
ARMv5TE ARM9E & ARM10E Superset of the ARMv4T
Extra inst. added for changing state
between ARM & Thumb
Enhanced multiply instructions
Extra DSP type instructions
Faster multiply accumulate
ARMv5TEJ ARM7EJ & ARM926EJ Java acceleration
ARMv6 ARM11 New multimedia instructions
 Instruction Set Architecture

Architecture Thumb DSP Jazelle Media TrustZone Thumb-2

v4T *

v5TE * *

v5TEJ * * *

v6 * * * *

v6Z * * * * *
v6T2 * * * * *
Day 1

Cortex Family
• ARM Cortex-A Series - Application processors for complex OS
and user applications
– ARM Cortex-A8, ARM Cortex-A9

• ARM Cortex-R Series - Embedded processors for real-time

systems
– ARM Cortex-R4(F)

• ARM Cortex-M Series – Embedded processors optimized for cost

sensitive applications, as Mobile devices
– ARM Cortex-M0, ARM Cortex-M1, ARM Cortex-M3
Which architecture is my processor?
Cortex-A8
• ARMv7-A Architecture
– Thumb-2
– Thumb-2EE (Jazelle-RCT)
– TrustZone extensions
• Custom or synthesized design
• MMU
• 64-bit or 128-bit AXI Interface
• L1 caches
– 16 or 32KB each
• Unified L2 cache
– 0-2MB in size
– 8-way set-associative
 Optional features
 VFPv3 Vector Floating-Point
 NEON media processing engine

 Super-scalar 13-stage pipeline