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Analog layout training

Schedule
1. Analog Introduction
2. Analog layout design flow
3. How to read schematic
4. Non-ideal effect on layout
5. Floorplanning
1. Analog introduction
What is Analog signal:
5V 1 1
2.5V
0 0
0V
Digital Signal Analog Signal
In digital world, signal are interpreted into just 2 stage: 0, 1 (on, off) In analog, things are different, everything count, any
For this example, everything above 2.5 V is considered 1, and changes in the signal can affect the output of the circuit,
everything below it considered as 0 system
Example:

A normal lamp, only have 2 state On/Off An audio amplifier, with each position the volume knob, the loudness change
1. Analog introduction
So, with that characteristic, analog system will be very sensitive to noise
Let see what happen when some noise introduce into these signal

5V 1 1
2.5V
0 0
0V
Digital Signal Analog Signal
Nah, no problem, still work fine  Wooooh, Shit happen 

Example:

Imagine if we just touch the contact lightly,


Just accidentally turn the volume knob -> Now that is loud ^^” everyone
the state of the lamp will stay the same, no
wake up
thing change
1. Analog introduction
With these characteristic, Analog will much more difficult to design, both schematic and layout

Schematic designer must know the behavior of all the component on the schematic, how it
react to even the slightest change on the signal
Layout designer, on the other hand, still have to know how to read a schematic, and know
all the non-ideal effect make the layout behave differently from what we expect on
schematic, and also know how to counter these non-ideal effect -> This is the purpose of this
training
2. Analog layout design flow
We does not need to understand how the circuit work, but have to know
This is the flow for basic, cell Schematic Analysis which components, which net are important and how to treat them
level layout.
Input to layout designer: From the schematic understanding, we floorplan (rough place) all the
- Schematic Floorplan
components, and we should also flan how the power and important
- Guideline from schematic signals are wired
designer (not always have) Floorplan review A peer review between designer, or a review from senior, schematic
Output: designer to find out if the floorplan is good enough for the schematic
- Layout with DRC/LVS cleaned
- All non-ideal effect consider Placement Detailed placement, with all guardring added
and have some measure for
them
Placement DRC DRC must be cleaned before any wiring happen

Routing Routing for all signal, recommend to wire all the important, hard to wire
signals first !!!
Most important step
Final DRC and LVS DRC and LVS for all cell

Review Whole cell review, especially wiring


3. Schematic Analysis
The first and also a very important step, this will effect much on how the floorplan going to good or not
First, we much know about the component, there are 3 basic one:

NMOS PMOS Capacitor


Resistor
MOS
This is a current pump This resist the flow of current This is a electronic reservoir
vdd vdd vdd
S S S
G G G
D D D

vss vss vss


3. Schematic Analysis
For easier to understand, you can imagine electric is like water.
Water will flow from place with higher place (vdd) to lower places (vss)
This is a current pump This resist the flow of current This is a electronic reservoir
vdd vdd vdd vdd
S S S
G G G
D D D

vss vss vss vss

The water flow from Vdd to vss is Resistor is the rock that block the This is the water reservoir
controlled by the MOS. water way, slow down the water In 1, the flow from the MOS have to be divided
By control the Gate, you can flow controlled by MOS and charge up the reservoir -> make it slower.
make the water flow faster or The bigger the rock, the slower the In 2. we turn off the MOS, now the connection
slower, or even shut the current current. from vdd is cut. But for the capacitor have been
off charged, It can use its store energy to discharge
the current through the resistor
3. Schematic Analysis
Base on the function of each device, circuit designer use them to make what they want. Some is simple, some is
complicated, layout designer must look at them and analyze which is important, and how to treat them.
Let us see one popular example
First, the blue one is call the current source, it decides the total current flow
through M1,2,3,4.
This only contain 1 NMOS or PMOS, control by the Vbias, the Vbias is fixed so
the current flow through it is fixed too.

vdd
S
Vbias
Vbias
D
S

This is just a simple element, you may only need to care about the current wiring, it have to big enough to accommodate
the current. And add dummies??? to reduce some non-ideal effect.
Anyway, if it goes with some other current source and make up an array, thing will be a little different

??? Dummies will be discuss in the floorplan phase, after we learn about non-ideal effect
3. Schematic Analysis The diode connection will transfer
This is current mirror, it contain 2 element: the current flow into it into
vdd voltage, and feed the voltage to
the current source.
S
If the current source and the
diode connection MOS have the
D
S same size (same W/L) the current
flow through will be the same,
Diode connection, the D and …and the current source hence the name current mirror
G node are tied together
In this, current mirror that act as the dynamic load of differential pair (M1, M2), we need to:
- Match the characteristic of these 2 MOS, they must be identical in everyway the current can be mirrored accurately
itail1

itail2

itail3

Beside being the active load of Diff. pair, they can be use to bias the whole circuit, by
iref

M1 M2 M3 M4 feeding the voltage of the diode connection to multiple current source.


This is called current array that provide bias current for other circuit, we need to:
- Try to math the device as much as possible. At least put them together, modify them
to have same finger size and put in array. Better to have interdigit or common centroid
placement.
- Put dummies at edge of array
3. Schematic Analysis
The differential pair, A differential pair consists of two MOS with common source, (S terminal
tied together). This is the most important devices in a differential amplifier.
Differential amplifier have one important characteristic, It can cancel out the common noise.
Let take a look at how thing go when there are a noise that infect both input signal:
Vo2
Vi1

Vi2

Vo1

In order to do this, the layout must be take extra care:


- Match the characteristic of these 2 MOS, they must be identical in everyway the current can be mirrored accurately.
Common centroid, interdigit is recommended
- The wiring for input and output must be matched too
3. Schematic Analysis
These basic structure make up the whole analog circuit, layout designer must analyze the schematic, pick out these tructure
and treat them properly. This is an example:

Current Current
source source
inverter

Diff pair
Diff pair

Current out
mirror

enb
3. Schematic Analysis
You will need to know the signal too, which of it is the current signal, voltage signal, which one is Diff signal…

Bias voltage

Current Current
bias bias
diff
in
out
Diff sig
diff Diff
Diff sig out
in
4. Non-ideal effect on layout
Idealy, the layout will behave just like what we expect in schematic.
Sadly, most of the time, that will not be the case, there are may non-ideal effect on layout that will make the layout behave
badly. Here, now, we will learn what are they and how to counter them.

items Affected elements Layout that should be noted

1 Parasitic R/C MOSFET, R, C Junction,wiring,ect..

2 STI dishing R Gate pattern in wide isolation area

3 STI stress MOSFET Distance from gate to A/A edge in


MOSFET

4 Well proximity MOSFET Distance of MOSFET to well-edge

5 Metal coverage MOSFET, R Wiring pattern near MOSFET or R

6 Gradient effect MOSFET, R Devices Placement


4. Non-ideal effect on layout
Parasitic R/C
In actual device, existence of parasitic capacitance cannot be avoided.

S D

Cgs Cgd

Csb Cdb

Any wiring, whether it by metal or poly will always have parasitic resistance and parasitic capacitance.
First about capacitance, as we learn from the schematic point, these capacitance can make the circuit slower. We don’t
want that, we have to reduce these parasitic.
4. Non-ideal effect on layout
Parasitic R/C
First, let see on MOS. These are example for MOS configuration and how they affect on the parasitic capacitance

Finger = 1 Finger = 1 Finger = 2 Finger = 4


Multi = 1 Multi = 4 Multi = 2 Multi = 1
S
D D Vth4
D
S S Vth5
D S S S
L D D Vth5
S D D D
S S Vth4
W S
S S

Cdtotal Cdb + Cgd Cdb + Cgd 1/2Cdb + Cgd 1/2Cdb +Cgd

As you can see, when divide the MOS in to many finger, we can reduce the D terminal capacitance. Just remember to keo
the total W/L of the MOS.
4. Non-ideal effect on layout
Parasitic R/C

Next, let’s see the cross session of MOS, and see some parasitic
Analog block Digital block

P+ N+ N+ N+ N+
Cdb
R R R

P sub R R R

- Substrate voltage level is affected by nearby digital block, this will create the
CLK body effect on MOSes, and change their performance
- This effect becomes remarkably at high frequency signal
Vsub
time
4. Non-ideal effect on layout
Parasitic R/C
Now, how to protect these analog devices
- Guard-ring should be arranged near noise source
- Analog block should be arranged far away as much as possible from noise source

Analog block Digital block OK

P+ N+ N+ N+ N+
Cdb
R R R

P sub R R R

Better
4. Non-ideal effect on layout
Parasitic R/C Next we talk about the parasitic capacitance between wiring

CLK

M2 line
CLK M1 line CLK

Sin M1 line M1 line Sin


Sin Sin signal

CLK

M3 line
CLK M1 line Noise introduce to sin

M2 line
signal by the CLK due to
GND M1 line M1 line the parasitic capacitance
Sin
Sin M1 line
Shielding line Shielding plane

When wiring, there are parasitic capacitance between line, extra care must be taken:
- Avoid crossing or run parallel Analog and CLK, digital line
- Shields are needed when crossing or parallel line.
- Shielding are needed for sensitive signal to prevent noise from other signal
Also remember, to make the wiring simple and short, it can reduce un-wanted capacitance
4. Non-ideal effect on layout
Parasitic R/C
The parasitic resistance of wiring will also have a lot of effects.
For example, let’s check this VSS wiring

On schematic, the VSS will have the same voltage=0 at any point
But due to the parasitic resistance, not anymore…

Better not use the min width in analog layout


These Voltage drop depend on the resistance value, the higher
the resistance, the higher the drop. We must have bigger metal
width to reduce these resistance
NG NG OK

M2 M2 M3

0.2V 0.3V 0.31V


0V
Vss 0.1V 0.2V 0.3V
4. Non-ideal effect on layout
items Affected elements Layout that should be noted

1 Parasitic R/C MOSFET, R, C Junction,wiring,ect..

2 STI dishing R Gate pattern in wide isolation area

3 STI stress MOSFET Distance from gate to A/A edge in


MOSFET

4 Well proximity MOSFET Distance of MOSFET to well-edge

5 Metal coverage MOSFET, R Wiring pattern near MOSFET or R

6 Gradient effect MOSFET, R Devices Placement


4. Non-ideal effect on layout
STI dishing
In actual device, surface of STI is not flat.

STI fabrication flow


4. Non-ideal effect on layout
STI dishing In actual device, surface of STI is not flat.→ Gate patterning size in
wide isolation area may be affected by STI dishing.
Example: poly-Si resistor array Improvement example

A A

A' A'

Ideal

Actual …or we can dumb these resistor at the edge


and use only the on in middle
A

A'
Resistance value shifts from designed value
4. Non-ideal effect on layout
items Affected elements Layout that should be noted

1 Parasitic R/C MOSFET, R, C Junction,wiring,ect..

2 STI dishing R Gate pattern in wide isolation area

3 STI stress MOSFET Distance from gate to A/A edge in


MOSFET

4 Well proximity MOSFET Distance of MOSFET to well-edge

5 Metal coverage MOSFET, R Wiring pattern near MOSFET or R

6 Gradient effect MOSFET, R Devices Placement


4. Non-ideal effect on layout
STI stress In actual device, MOSFET is affected by distance from gate to
A/A(active area) edge.

Stress strength
Sa Sb

L position
Stress Stress

Stress = 1/(Sa + (L/2))


+ 1/(Sb + (L/2))
Influence of STI stress decreases with increase in Sa and Sb

Counter, add Mos at the edge as dummies to reduce the effect


on the active MOS in the middle
4. Non-ideal effect on layout
items Affected elements Layout that should be noted

1 Parasitic R/C MOSFET, R, C Junction,wiring,ect..

2 STI dishing R Gate pattern in wide isolation area

3 STI stress MOSFET Distance from gate to A/A edge in


MOSFET

4 Well proximity MOSFET Distance of MOSFET to well-edge

5 Metal coverage MOSFET, R Wiring pattern near MOSFET or R

6 Gradient effect MOSFET, R Devices Placement


4. Non-ideal effect on layout
Well proximity In actual device, well-dopant density changes according to distance from well
implantation edge.

[gate – well edge] spacing ↓, Vt↑, Id↓

Example: It's assumed that these 3 MOSFETs have same well

VthL ≠ VthM ≠ VthR

STI fabrication flow


. STI formation
The counter will be add
dummies at the edge,
and balance spacing
. STI formation between devices and
- photo litho well in both up-down,
- ion implant left-right
4. Non-ideal effect on layout
items Affected elements Layout that should be noted

1 Parasitic R/C MOSFET, R, C Junction,wiring,ect..

2 STI dishing R Gate pattern in wide isolation area

3 STI stress MOSFET Distance from gate to A/A edge in


MOSFET

4 Well proximity MOSFET Distance of MOSFET to well-edge

5 Metal coverage MOSFET, R Wiring pattern near MOSFET or R

6 Gradient effect MOSFET, R Devices Placement


4. Non-ideal effect on layout
Metal coverage Wiring pattern above or near pair elements should be symmetry
VoutL VoutR Intention: balance noise/coupling on pair elements net
VgL D D VgR
Normal
S S Vin
L

VSS
VinR

VinL M1 M VinL M1 M
VinR
VoutL 1D VoutR VoutL S D
1D S
S D S
Noise/cou
Vin pling
VoutR L

dummy wiring

VinR
4. Non-ideal effect on layout
Gradient effect

On layout, Gradient effect the matching of device greatly (exp: thermal, noise, process gradient…) A B
Example: there is a thermal source at top Left corner of the circuit.

A A B

B B A

NG OK
Thermal Effect on MOS A is much bigger than Split MOS A and B in to 2 MOS with half W, and
MOS B place them in common centroid theme.
=> the total effect of the thermal source on both
MOS is the same
4. Non-ideal effect on layout A B

Gradient effect
Other common centroid placement

A and B are placed in common centroid.


A B B A Total gradient effect is the same, but this will
result in non symmetry in wiring, and othere
effect like well proximity, STI stress…

A and B Not common centroid, but approximately.


A B A B But It is symmetry, and easier to have matching
wiring
This is call interdigitation placement

If Possible, improve pattern of common centroid


for best matching.
A B B A

B A A B
5. Floorplanning Current source
Basic schematic element

DMM

DMM
itail

A
itail
Vbias
S

DMM
DMM
itail

A
Example current source A with multi = 4

DMM

DMM
Dummies should be added to reduce the STI stress,

A
itail
WPE effect.

Tail, Vss wiring should be big to reduce parasistic


capacitance.
5. Floorplanning Differential Pair A/B or current mirror
Basic schematic element
A B
- These need to be matching on device level

A
B
Scheme 1
DMM

DMM

Scheme 2
A
B

DMM

DMM
A

A
B

B
DMM

DMM
A

Interdigitation placement for good device matching,


have simpler wiring, less parasitic capacitance
Common centroid placement for best device matching.
But have complex wiring, and higher parasitic capacitance
5. Floorplanning Current Array
Basic schematic element
Example current array, with mA = 1, mB =2, mC =4

DMM

DMM
A B C
Ok

C
DMM

DMM
A
Good

B
C

C
B

C
DMM
DMM
Ok

B
C

C
DMM

DMM

DMM
DMM
Better

DMM
DMM

C
2. Fundamental of analog layout
Floor-planing
 Schematic analyze:  Layout floor-plan:
? schematic ? Trade-off between systematic
specs factors and schematic alike
(change mos W/L, add dmy... →
slightly different in simulation
result)
? Important devices: pair elements, ? Important devices: grouping them,
sensitive caps, inductor, RF... choose suitable placement pattern
? Important net: in/out, pair routing, after consider schematic specs
current density on net (note by ? Important net: in/out direction,
schematic designer) … metal policies, metal width,
shielding, power pattern...
? Always think of possible
smallest size
5. Floorplanning
Floor-planing
Example:

 Schematic analyze:
? schematic specs: case 1, case 2
(different expects for same
schematic will be explain after
grouping important devices)
? Important devices: DIFF pairs,
current MIRRor pairs, PM5
? Important net: [INN-INP], [vn-vp],
tail, OUT

tail OUT
vp vn
5. Floorplanning
Floor-planing Example:

 Layout floor-plan:
? Schematic specs: case 1, case 2
(different expects for same
schematic will be explain after
grouping important devices)
? Important devices: grouping
[PM1_DIFF-PM2_DIFF],
[N_MIRRIN-N_MIRROUT], PM5
(simply place as schematic)
? Important net: pin placement for
in/out direction (if don't know,
tail commonly in-left, out-right ), [INN-
vp INP], [vn-vp], tail, OUT, power
vn patterns. Plan draft line for
OUT
important nets if possible
5. Floorplanning
Floor-planing Example: red highlight is schematic specs
Case 1:
? good operation speed, better gain →
low cap
 DIFF: Interdigitated placement, simple
wiring
PM5 

MIRR: Interdigitated placement
PM5-DIFF-MIRR: place on same vertical
symmetry axis if possible (if not, increase
metal width for compensation of reduce
parasitic resistor)
PM1_DIFF.1 PM1_DIFF.1  Has individual guard-ring for noise isolation
 Add side dummy mos for PM5/DIFF/MIRR
PM2_DIFF.2 PM2_DIFF.2
to reduce side effects
? Reuse on multiple layout → don't
tail has fix pins location
MRIN
MROUT MROUT
vp  In/out net stretch to both sides if possible(if
vn not, simply in-left, out-right)
OUT  pwr/gnd lines place as top/bottom
5. Floorplanning
Floor-planing Example: red highlight is schematic specs
Case 2:
? High accuracy (ADC, BRG...) →
matching
 DIFF: common-centroid, balance wiring
 MIRR: Interdigitated is OK, common-
PM5 centroid is better.
 PM5-DIFF-MIRR: place on same vertical
symmetry axis if posible (if not, increase
metal width for compensation of reduce
PM1_DIFF.1 parasitic resistor)
 Has individual guard-ring for noise isolation
PM2_DIFF.2  Add side dummy mos for PM5/DIFF/MIRR
to reduce side effects
MRIN
PM1_DIFF.1
? Reuse on multiple layout → don't
tail has fix pins location
PM2_DIFF.2 MROUT MROUT vp  In/out net stretch to both sides if possible(if
vn not, simply in-left, out-right)
OUT  pwr/gnd lines place as top/bottom
5. Floorplanning
Let’s go back to the example from schematic reading

Current Current
source source
inverter

Diff pair1
Diff pair2

Current out
mirror

enb
5. Floorplanning
Diff pair1/2 Common centroid placement
Current Current
source 1 source 2 Current mirror Interdigit placement

Diff Res Interdigit placement

Diff Diff Output Current array Only Place together and have dummies
pair1 pair2 Inverte
r
I have all the device that is connected to VDD gather on the
TOP, VSS to the bottom, so It will be easy to have PG wiring.
diff
Current
in Each pair, current array have its own guardring to reduce
mirror cross noise between devices.

diff
in
Diff res