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Verilog Digital System Design

Z. Navabi, McGraw-Hill, 2005

Chapter 0
Course Description
and Policy

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 1
Course Description
and Policy
NORTHEASTERN UNIVERSITY
Electrical and Computer Engineering
ECE G356
Digital System Design and Interfacing with Verilog
Summer 2006
Course Description and Outline
9:00-12:00 Friday
Dr. Zainalabedin Navabi
navabi@ece.neu.edu

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 2
Course Description
and Policy
Automatic design and verification of complex digital
systems with Verilog is the main course objective. Using
Verilog for a design that consists of several parts that
include controllers, sequential and combinational parts
is focused. Design description from transistor level to
software interface will be discussed. Students will learn
details of hardware of processor architectures and their
peripherals. Testbench development and assertion
verifications will be discussed.
Verilog Digital System Design
January 2006 Copyright Z. Navabi, 2006 3
Course Description

and
Course Material:
Policy
 Main Text: "“Verilog Digital System Design: Register
Transfer Level Synthesis, Testbench, and Verification”;
2006; McGraw Hill Text; ISBN: 0070144564-1.
 Reference: “IEEE Std. 1364-2001, Hardware Description
Language Based on the Verilog Hardware Description
Language,” IEEE, New Jersey, 2001. Available on NEU
Library Electronic References.
 Software: Verilog Simulator: ModelSim; Design
Environment and Synthesis: Quartus II.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 4
Course Description
and Policy
 Grading:
 Six Regular Homeworks: 40%
 Design Homework: 15%

 Midterm: 20%

 Final: 25%

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 5
Course Description
 Lecture 1:
and Policy
 Introduction
 Course Contents
 Goals
 Course Procedures
 RTL Logic design using discrete logic
 Problem Specification
 Datapath
 Controller
 Digital System Design Automation with Verilog
 Digital Design Flow
 Verilog HDL

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 6
Course Description
 Lecture 2:
and Policy
 Register Transfer Level Design with Verilog
 RT Level Design
 Elements of Verilog
 Component Description in Verilog
 Testbenches
 Lecture 3:
 Tools and Environments
 HDL Simulation
 Design Entry
 Pre-synthesis Simulation
 Synthesis
 Post-Synthesis Simulation

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 7
Course Description
 Lecture 2:
and Policy
 Register Transfer Level Design with Verilog
 RT Level Design
 Elements of Verilog
 Component Description in Verilog
 Testbenches
 Lecture 3:
 Tools and Environments
 HDL Simulation
 Design Entry
 Pre-synthesis Simulation
 Synthesis
 Post-Synthesis Simulation

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 8
Course Description
and Policy
 Lecture 4:
 Verilog Language Concepts
 Characterizing Hardware Languages
 Module Basics

 Verilog Simulation Model

 Compiler Directives

 System Tasks and Functions

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 9
Course Description
and Policy
 Lecture 5-6:
 Combinational Circuit Description
 Module Wires
 Gate Level Logic

 Hierarchical Structures

 Describing Expressions with Assign Statements

 Behavioral Combinational Descriptions

 Combinational Synthesis

 Exam Review

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 10
Course Description
and Policy
 Lecture 7: TEST 1
 Midterm Exam
 Verilog HDL
 Simulation Model

 Tools

 Combinational Circuits

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 11
Course Description
and Policy
 Lecture 8-9:
 Sequential Circuit Description
 Sequential Models
 Basic Memory Components

 Functional Registers

 State Machine Coding

 Sequential Synthesis

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 12
Course Description
and Policy
 Lecture 10:
 Component Test and Verification
 Testbench
 Testbench Techniques

 Design Verification

 Assertion Verification

 Text Based Testbenches

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 13
Course Description
and Policy
 Lecture 11:
 Detailed Modeling
 Switch Level Modeling
 Strength Modeling

 MOS, CMOS

 Dynamic and static flip-flops

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 14
Course Description
 Lecture 12:
and Policy
 RT Level Design and Test
 Sequential Multiplier
 von Neumann Computer Model
 Lecture 13:
 RT Level Design and Test
 CPU Design and Test
 Processor RTL Architecture
 CPU Testing
 Text Based Testing
 Lecture 14:
 Processor Devices
 Cache
 Serial Interface
 DMA

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 15
Book Chapters
 Chap. 1 gives an overview of digital design process and the use of
hardware description languages in this process. Simulation, synthesis,
formal verification and assertion verification are discussed in this
chapter.

 Chap. 2 shows various ways hardware components can be


described in Verilog. The purpose of this chapter is to give the reader a
general overview of the Verilog language.

 Chap. 3 discusses the complete Verilog language structure. The


focus of the chapter is more on the linguistic issues and not on
modeling hardware components. A general understanding of the
language is necessary before it can be used for hardware modeling.
Writing Verilog for describing hardware is discussed in the chapters
that follow this chapter.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 16
Book Chapters
 Chap. 4 starts with gates and ends with high level
Verilog constructs for description of combinational
circuits. Concurrency and timing will be discussed in the
examples of this chapter. Except for specification of
timing parameters, codes discussed in this chapter are
synthesizable. A section in this chapter presents rules for
writing synthesizable combinational circuits.
 Chap. 5 discusses modeling and description of
sequential circuits in Verilog. The chapter begins with
models of memory and shows how they can be specified in
Verilog. Registers, counters, and state machines are
discussed in this chapter. A section in this chapter presents
rules for writing synthesizable sequential circuits.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 17
Book Chapters
 Chap. 6 is on writing testbenches in Verilog. The
previous two chapters discussed Verilog from a hardware
design point of view, and this chapter shows how
components described as such can be tested. We talk
about data generation, response analysis, and assertion
verification.
 Chap. 7 covers switch level modeling and detailed
representation of signals in Verilog. This material is geared
more for those using Verilog as a modeling language and
less for designers. VLSI structures can be described by
Verilog constructs discussed here.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 18
Book Chapters
 Chap. 8 shows complete RTL design
flow, from problem specification to test. We
show several complete examples that take
advantage of material of Chapters 4, 5, and
6 for description, simulation, verification,
and synthesis of digital systems. Examples
in this chapter take advantage of text IO
facilities of Verilog for storing test data and
circuit responses.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 19
Book Chapters
 Appendix A shows Verilog keywords.
 Appendix B lists commonly used system tasks and briefly
describes each task.
 Appendix C lists Verilog compiler directives and explains
their use.
 Appendix D presents the standard IEEE Verilog HDL
syntax. Language constructs terminals and non-terminals
are presented here in a formal grammar representation.
 Appendix E presents the OVL assertion monitors. After a
brief description of each assertion monitor its parameters
and arguments are explained.

Verilog Digital System Design


January 2006 Copyright Z. Navabi, 2006 20