UNIT I

Introduction-8086 Architecture-Block Diagram, Register

Organization, Flag Register, Pin Diagram, Timing and
Control Signals, System Timing Diagrams, Memory
Segmentation, Interrupt structure of 8086 and Interrupt
Vector Table. Memory organization and memory banks
accessing.
Microprocessor

 Microprocessor is an Integrated circuit that

contains all functions of a central processing unit
of a computer.

 Single integrated chip containing millions of

very small components including transistors,
resistors and diodes that work together.
General Microprocessor
Address bus, data bus, control are called system bus
Address bus:
 It is a group of wires or lines that are used to transfer
the addresses of Memory or I/O devices.

 It is unidirectional.

 The width of the address bus is determined by the

size of the memory that should be addressed by the
system.

 The address is always specified by the processor.

Data bus:
 As name tells that it is used to transfer data within
Microprocessor , Memory/Input or Output devices.

 The width of the data bus is determined by the size of

the individual memory block

 It is bidirectional as Microprocessor requires to send

or receive data.

 The data bus also works as address bus when

multiplexed with lower order address bus.
Control bus:
 Microprocessor uses control bus to process data, that
is what to do with the selected memory location.
Some control signals are Read, Write and Opcode
fetch etc.

 Various operations are performed by microprocessor

with the help of control bus.

 This is a dedicated bus, because all timing signals

are generated according to control signal.
Why the data bus is Bi-directional?

The microprocessor is to fetch (read) the data

from memory (or) input device for
processing and after processing it has to
store (write) the data to memory (or) output
devices. Hence the data bus is Bi-directional
Why address bus is Uni-directional?

The address is an identification number used

by the microprocessor to identify (or) access
a memory location (or) I/O devices.
It is an output signal from the processor.
Hence the address bus is Uni-directional.
Features of 8086:
 The 8086 is a 16-bit microprocessor.

 The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.

 The 8086 has a 20-bit address bus, so it can directly access 220 or
10, 48,576 (1MB) memory locations. Each of the 1MB memory
locations is byte wide. Therefore, a 16-bit word is stored in two
consecutive memory locations.

 The 8086 can generate 16-bit I/O address, hence it can access
216=65536 I/O ports.

 The 8086 provides fourteen 16-bit registers.

 The 8086 has multiplexed address and data bus (AD15-AD0)
which reduces the number of pins needed, but does slow down the
transfer of data.

 The 8086 requires clock with a 33% duty cycle to provide

optimized internal timing.

 The 8086 microprocessor available in three clock rates: 5 MHz

(8086), 8 MHz (8086-2) and 10 MHz (8086-1).

 The Intel 8086 is designed to operate in two modes: minimum

mode and maximum mode.

 It requires +5V single power supply.

 HMOS technology
 6-byte Queue
8086 Architecture
The complete architecture of 8086 can be
divided into two parts

 Bus interface unit (BIU)

 Execution unit (EU)

Bus interface unit (BIU)
 Interface with other devices
 It does perform all work related to memory
 Fetching data from memory
 Storing data to memory

 This unit is responsible for establishing

communications with external devices and
peripherals including memory via
Execution unit (EU)
 General purpose registers
 Special purpose registers
 Operand register
 Instruction register & decoder
 ALU
 Flags
Register organization of 8086
8086 has power full set of registers known as General
purpose registers and special purpose registers

 All of them are 16-bit registers

 The general purpose registers, can be used as either

8-bit or 16-bit registers.

 The special purpose registers are used as segment

registers, pointers, index or as offset storage registers
for addressing modes.
AX AH AL CS SP

BP
BX BH BL SS
FLAGS / PSW SI
CX CH CL DS
DI

DX DH DL ES IP

General data Segment Point & index

registers registers registers
Segment registers
CODE (64K)

DATAS1(64K)
CODE

DATA
DATAS2 (64K)
STACK

EXTRA STACK(64K)

Segment registers
Memory
Segmentation :

 It the process in which the main memory of a

computer is divided in to different segments and
each segment has its own base address.

 Segmentation is used to increase the execution

speed of system. So that, processor can able to
fetch and execute the data from memory easily and
fasetly
 8086 address a segmented memory.

 The complete 1 megabyte memory is divided into

16 logical segments.

 Each segment contains 64K bytes of memory.

 There are 4 segment registers

Code segment (CS)
Data segment (DS)
Extra segment (ES)
Stack segment (SS)
 Code segment: CS +IP

 Stack segment: SS+SP/BP

 Data segment: DS+BX/SI

 Extra segment: ES+DI

 Physical address= Base address + Offset address

 Address generation circuit

Physical address = Segment address X 10h +

(20-bit) Offset address
Memory segmentation
Cs(64K)

SS(64K)

DS(64K)

ES(64K)
Queue
 BIU also contain an instruction queue. When the EU
executes instructions, the BIU gets up to 6-bytes of
the next instruction and store them in the instruction
queue and this process is called instruction prefetch.
 This is a process to speed up the processor.
Flag register
Memory banking
Memory banking
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
Address Data type BHE A0 Bus cycles Data lines used

0000 BYTE 1 0 ONE D0-D7

0000 WORD 0 0 ONE D0-D15

0001 BYTE 0 1 ONE D7-D15

0 1 FIRST D0-D7
0001 WORD
1 0 SECOND D7-D15
PIN Diagram of 8086
Modes of 8086
It can be operated in two modes
 Minimum mode
 Maximum mode
Minimum mode
 If one processor along with memory, input & output
devices are connected to the system bus then that
mode are called minimum mode

 It is called single Processor system

 Primarily used in simple applications
 It is responsible for generating all control signals on
its own for memory and I/O
 Pin-33 (MX/MN) is high(i.e, to 5V) to enable this
mode
What is maximum mode:
If more than one processor along with memory, input &
output devices are connected to the system bus then that
mode are called maximum mode or multi processor
system.

 Additional processors can be connected. eg:

8087arithmetic co-processor

 External bus controller responsible for generating all

control signals for memory and I/O

 It is used for complex and large applications

 Pin-33 (MX/MN)is grounded to enable this mode(i.e, 0V)

 Power supply (pin:40 & 1,20)
It uses 5V DC supply at VCC and uses ground at VSS for
its operation.

 Clock signal (pin:19)

Clock signal provides timing to the processor for
operations. Its frequency is different for different
versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus (pin:2-16)
AD0-AD15. These are 16 address/data bus. AD0-AD7
carries low order byte data and AD8-AD15 carries
higher order byte data. During the first clock cycle,
it carries 16-bit address and after that it carries 16-
bit data.

Memory address or I/O port: whenever ALE =1

Data : whenever ALE=0
High impedance state: during a HOLD acknowledge
 Address/status bus (pin:35-39)
A16-A19/S3-S6. These are the 4 address/status buses.
During the first clock cycle, it carries 4-bit address
and later it carries status signals.
S6: always remains a logic 0
S5: indicate condition of IF flag bits
S3,S4: shows which segment is accessed during
current bus cycle
S3 S4 Function
0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data segment
 Ready (pin:22)
It is an acknowledgement signal from I/O devices that
data is transferred. It is an active high signal. When
it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.

 RESET (pin:21)
It is used to restart the execution. It causes the
processor to immediately terminate its present
activity. This signal is active high for the first 4
clock cycles to RESET the microprocessor.
 INTR (pin:18)
It is an hardware interrupt request signal, which is sampled
during the last clock cycle of each instruction to
determine if the processor considered this as an interrupt
or not.
 NMI (pin-17)
It stands for non-maskable interrupt . It is an edge triggered
input, which causes an interrupt request to the
microprocessor.

 TEST (pin-23)
This signal is like wait state . When this signal is high, then
the processor has to wait for IDLE state, else the
execution continues.
 S7/BHE (pin:34)
BHE stands for Bus High Enable. and used to indicate
the transfer of data using data bus D8-D15. This
signal is low during the first clock cycle, thereafter it
is active.
Status of S7 always high
 QS1 and QS0 (pin:24&25)
These are queue status signals These signals provide
the status of instruction queue.
QS0 QS1 status
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
 S0, S1, S2 (pin:26-28)
These are the status signals that provide the status of
operation, which is used by the Bus Controller 8288
to generate memory & I/O control signals.

S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 passive
 M/IO (pin:28)
This signal is used to distinguish between memory and I/O
operations. When it is high, it indicates I/O operation and when it
is low indicates the memory operation.

 WR (pin:29)
It stands for write signal. It is used to write the data into the memory
or the output device depending on the status of M/IO signal.

 HLDA (pin:30)
It stands for Hold Acknowledgement signal. This signal
acknowledges the HOLD signal.

 HOLD(pin:31)
This signal indicates to the processor that external devices are
 ALE (pin:25)
It stands for address enable latch A positive pulse is generated
each time the processor begins any operation. This signal
indicates the availability of a valid address on the
address/data lines.

 DEN (pin:26)
It stands for Data Enable. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data
from the address/data bus.

 DT/R (pin:27)
It stands for Data Transmit/Receive signal. It decides the
direction of data flow through the transreceiver. When it is
high, data is transmitted out and vice-versa.
Interrupts of 8086
 The meaning of 'interrupts' is to break the sequence
of operation.
While the Microprocessor is executing a
program, an 'interrupt' breaks the normal sequence
of execution of instructions, diverts its execution to
some other program called Interrupt Service
Routine (ISR)

There are two methods to obtain input

Polling
Interrupt
 In polling method, the microprocessor continuously
monitors the status of a given device; when the status
condition is met, it performs the service. After that, it
moves on the next device until each one is serviced.

 In interrupt method, when ever any device needs

service from microprocessor, the device notifies to
processor by sending signal (called interrupt)
Types of Interrupts
 Hard ware Interrupts: used to handle external
hardware peripherals, such as key board, mouse,
hard disk, floppy disk, DVD drives & printers

 Maskable Interrupt are connected through INTR

(pin-18)
 Non-Maskable Interrupt are connected through NMI
(pin-17)
 These two are external interrupts

Maskable Interrupt :The programmer can choose to

mask specific interrupts and re-enable them later
 Non-Maskable Interrupt: The programmer cannot control
when non-maskable interrupt is served.

Non-maskable interrupt occur the processor has to stop

the main program to execute the NMI service routine and
comes back main program

Non maskable interrupt has highest priority among all

external interrupts

 Used during power failure

 Used during critical response time
 Used during non-recoverable hardware errors
 Used during memory parity errors
 Software Interrupts: Used by operating systems to provide
hooks into various functions.

Used as a communication mechanism between different parts of

a program

Total 256 interrupts (00H to FF H) processing of an interrupt by

the processor.

 Execute the INT instruction

 Interrupts the INT instruction during the assembly time
 Moves the INT instruction to the vector table
 Vector table occupies location 000 H to 3FF H of the program
memory
 It contains the code segment (CS) and instruction pointer (IP)
for each kind of interrupt
Interrupt vector Table
Software interrupt-Type 0 through 255

 The 8086 INT instruction can be used to trigger the

8086 to do any one of the 256 possible interrupt
types. The desired interrupt type is specified as a
part of the instruction.
Type 0: Divide-by-zero Interrupt
 The 8086 will automatically do a type 0 interrupt if
the result of a DIV operation or an IDIV operation is
too large to fit in destination register.

 For a type 0 interrupt, the 8086 pushes the flag

register on stack, resets IF and TF and pushes the
return addresses on stack.
Type 1: Single step interrupt
 The use of single step execution feature is found in
some of the monitor and debugger programs.

 When a system to single step, it will execute one

instruction and stop. Then examine the contents of
registers and memory locations.
Type-2: Non-maskable interrupt

 The 8086 will automatically do a type 2 interrupt

response when it receives a low to high transition on
its NMI pin.

 When ever it does a type 2 interrupt, the 8086 will

push the flags on the stack, reset TF and IF, and
push the CS value and the IP value for the near
instruction on the stack.
Type-3: Breakpoint interrupt
 The type 3 interrupt is produced by execution of the
INT3 instruction. The main use of the type 3
interrupt is to implement a breakpoint function in a
system.

 Whenever we insert a breakpoint, the system

executes the instructions up to the breakpoint and
then goes to the breakpoint procedure.
Type 4: Overflow interrupt

 The 8086 overflow flag will be set if the signed

result of an arithmetic operation on two signed
numbers is too large to be represented in the
destination register or memory location
General Bus Cycle For 8086
Timing Diagram
END