DFT2017

Lifetime Reliability Characterization of N/MEMS

Used in Power Gating of Digital Integrated Circuits

Haider Alrudainy, Rishad Shafik, Andrey Mokhov

and Alex Yakovlev,

Micro System Design Group, School of EEE,

Newcastle University, UK

H.m.a.alrudainy@ncl.ac.uk, Rishad.Shafik@ncl.ac.uk, Andrey.Mokhov@ncl.ac.uk,

Alex.Yakovlev@ncl.ac.uk

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 DFT2017

Agenda:
 Introduction
 Background
 Motivations
 Modelling
 Proposed Architecture
 Results
 Conclusion and future work
 References
2
 Introduction DFT2017
Power Density Trend
CMOS challenges: 1E+03
Active Power Density

Power Density (W/cm2)

1E+02
 Power/energy challenge 1E+01
1E+00
1E-01
 Power density critical 1E-02
1E-03
 Energy consumption too high for 1E-04
Passive Power Density

 portable devices 1E-05

1
0.01 0.1
 Baseband processor Gate Length (μm)
 Biomedical implants Source: B. Meyerson (IBM) Semico Conf.,
January 2004
 Wire sensor network
 Leakage power approaches active power
25

Normalized Energy/cycle
20

15

 Functionality challenge 10
Etotal

 Device in harsh environments 5 Edynamic

Eleak
 High temperature 0.1 0.2 0.3 0.4 0.5
3
 Radiation-hard Vdd (V)
 Background DFT2017

N/MEM switches: Background, operation principle, FEA simulation

 Many investigatory research are currently exploring the potential use of these switches as the
means of power gating devices of digital integrated circuits as Illustrated in table 1.

 This attributed to their zero-leakage energy compared to that of CMOS power transistors as
shown in Fig. 1.
 Fig. 2 shows the FEA simulation of the adopted MEMS

Table 1: Features of the N/MEMS based power gating approaches.

Fig. 1 shows operation principle of N/MEMS

Fig. 2: Demonstrates the: (a) FEA-simulated pull-in voltage;

(b) simplified sketch, symbols L, W, LA, and WA denote,
respectively, spring (length/width), and actuation area
(length/width) 4
 Modelling DFT2017

 To model and capture the physical behaviour of MEMS accurately, COMSOL multiphysics
tool has been used in our work. Parameteric sweep analysis Has been performed to calculate
the following points:
 Structure stiffness
 Damping analysis
 Energy-Latency Analysis of N/MEMS

Fig. 3: A comparison of the pull-in voltage for three different gaps

obtained from full finite element model and the analytical model. Fig. 4: impact of increasing structure damping coefficient on
bouncing and contact damping based 4-terminal MEMS,
A=450um2, g0=200nm, gd=40nm, stiffness=150N/m, mass=0.29
× 10−10 .
Table II: Current and scaled MEM relay physical parameters based on COMSOL multiphysics tool.

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 Modelling DFT2017

Fig. 5: Illustrates that: (a) switching energy based FEA at g0=200nm and A=450um2 as a function of gd and resonant frequency
(w); (b) Tmech: as a function of gap ratio and resonant frequency obtained from 3D FEA at A=450um2; (c) Tmech: of the scaled
relay at g0=40nm and A=45um2 as a function of gd and resonant frequency; (d) switching energy of the scaled relay.
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 Modelling DFT2017
Device
o dimensions COMSOL
o geometry multiphysics
o Material 3D FEA
o etc. simulator

VHDL code
-Parametric sweep o ARM-M0
Contact -Transient analysis microprocessor
modelling -Frequency analysis o FIR filter
o FB (DSP, RF, ….)

o Stiffness (k)
Extract Device o Damping (b)
parameters o Mass(m) Synopsis-
o Pull-in Voltage (Vpi) simulator
o Mechanical time synthesis
o Switching energy
o etc.

Verilog-AMS
Optimize
(Electrical and o Dynamic and
mechanical static power
lumped model) [1] o Area

Results
o Total energy Cadence
o Timing simulator
o etc.
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 Switch Simulator Based on (FEA) DFT2017

VS0
Fele 0

Source
Lumped mechanical parameters, 3D (FEA) based
Fvdw 0
𝑆𝑘 Z0
Scaling
factors

Vg1 VS1
θ𝑏

Lumped electrical parameters

Relay

Φ𝑚 Fele 1

Body
fabricated/predicted
Fvdw 1
Verilog-AMS
on COMSOL

Verilog-AMS
Z1

Based on

Vg2

Gate
MEMS/ NEM

VSN
Fele N
Fvdw N
ZN

Vg2
Mechanical contact

Drain
Fig. 7: Graphic illustration of the hierarchical model of the switch simulator. The highlighted regions represent the electrical and
mechanical lumped parameters, which is highlighted regions represent the electrical and mechanical lumped parameters, which is
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written in Verilog-AMS and co-simulated in The Spectre spice tool.
 Reliability Characterizations DFT2017

 Natural and resonant frequency

 The calculated natural frequencies using COMSOL tool of the relays in [3], [16], and
[17] are equal to 1.2 106 Hz, 146 106 Hz, and 179 106 Hz, respectively.
 These values of frequencies represent the maximum allowable power gate switching
as the N/MEMS will oscillate beyond these frequencies, thereby causing an operation
failure.
 Surface Stress
 Contact Damping/Bouncing
Postion (nm) Postion (nm)
T 𝑉𝑑𝑑 (volt) 𝑉𝑑𝑑 (volt)
T

Time(us) Time(us)
τ𝑚𝑒𝑐ℎ.τ𝑠𝑡𝑎𝑏𝑙𝑒τ𝑒𝑣𝑎𝑙𝑢𝑎𝑡𝑒 τ𝑚𝑒𝑐ℎ. τ𝑠𝑡𝑎𝑏𝑙𝑒
(a) (b)
Fig. 7: Resonant frequency of the 2-spring N/MEMS
Fig. 6: Contact bouncing impact when using ramped Vdd (a) safe bouncing;
(b) unstable bouncing cause operation failure of power-gated circuits.
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 Proposed Reliable Approach DFT2017

VDD Ø = VDD N/MEMS

S
G S Metal
Insulator
D B Charge
G
Pump Interconne
D
G cts
D N/MEMS
S
CMOS
layer
Silicon
(b)
Latches Latches Ø = VDD
CP
Data D Q Combinational D Q
Output
circuits N/MEMS

Combinational
Sleep=0 circuits
Clock
(a) (c)
Fig. 8: Illustrates that (a) proposed architecture; (b) 3D schematic of N/MEMS 10
 Results: DFT2017
Table III: Energy consumption for 32-tap FIR filter at various asynchronous PG setups .

 In our experiment a complex combinational circuit, such as 32-tap FIR filter, is used due to the fact that, unlike CMOS
power switch N/MEMS favour a complex design architecture coupled with low duty cycle
implementations
 It should be noted that our proposed approach only differs from [3] by using a ramp supply voltage with
various T.
 These results indicate that at low data rate our approach can achieve greater energy savings by about 9%
compared to the previously reported results
 This can, firstly, be attributed to completely cutting off the leakage dissipation during the idle state. Secondly, the dynamic
energy of the FIR filter is significantly minimized due to mitigation of the contact bouncing and current rushing by slow
charging of the load capacitance.
 However, increasing the data rate will lead to increase switching energy of the MEMS-based power gating which outweigh
its leakage power savings, as illustrated in Table III.
 It should be noted that in this experiment the damping coefficient was chosen to be equal to 50 ×10−8 N.s/m. Reducing
the damping coefficient to 50 ×10−8 N.s/m has led the simulator to diverge, thereby no useful results are obtained due
to the large bouncing time (floating). 11
 Results: DFT2017

 Asynchronous 8/-32 FIR filter

Vdd Vdd

MEMS power switches MEMS power switches

(S1) (S2)
Vdd PD1 Vdd PD2

32 64 32 32 32 32
Multiplier Accumulator
D Flip-flop D Flip-flop D Flip-flop
Data_in Data_out

EN0 EN1 EN2

MEMS-based MEMS-based
Delay line Delay line
req_in req_0 req_1 req_out
CP H/S CP H/S
Pipeline
Controller Ctr1 Ctr2
ack_out ack_in
ack_0 ack_1

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 Conclusion: DFT2017

Conclusion:

 We presented an investigation into lifetime reliability issues of N/MEMS based

power controllers of digital integrated circuits.

 This study demonstrated the limitations at which N/MEMS can be adopted without
impact any potential failure of the power-gated circuits.

 Furthermore, this study showed the threshold at which N/MEMS can achieved
greater energy saving compared to that of CMOS transistor.

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 DFT2017

References
[1] H. Alrudainy, A. Mokhov, and A. Yakovlev, “A scalable physical model for nano-electro-mechanical
relays,” in Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International
Workshop on, pp. 1–7, Sept 2014

[2] D. Lee, W. Lee, C. Chen, F. Fallah, J. Provine, S. Chong, J. Watkins, six-terminal nem relays,” Computer
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 32, pp. 653–666,
May 2013.

[3] M. Spencer, F. Chen, et al., "Demonstration of integrated micro-electro-mechanical relay circuits for
Source

VLSI applications," IEEE Journal of Solid-State Circuits, vol. 46, pp. 308-320, // 2011.

[4] M. Henry and L. Nazhandali, “From transistors to mems: Throughputaware power gating in cmos
circuits,” in Design, Automation Test in rope Conference Exhibition (DATE), 2010, pp. 130–135, March
2010.
[5] B. Amelifard and M. Pedram, “Design of an efficient power delivery network in an soc to enable
dynamic power management,” in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE
International Symposium on, pp. 328–333, Aug 2007.
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