Embedded System Design Methodology

EE382V:
Embedded System Design and Modeling
Lecture 4 – System Design Flow and Methodology
Andreas Gerstlauer
Electrical and Computer Engineering
University of Texas at Austin
gerstl@ece.utexas.edu
Lecture 4: Outline
• SpecC system design methodology

• From specification to implementation
– Specification
– System design
– Processor design
• Models and transformations
– Specification model
– Computation model
– Communication model
– Implementation model
EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 2

System Design
µProcessor
Control Pipeline IF FSM
IP RAM IP Netlist
Memory Comp. State
PC
Interface Interface IR
Bus Control Datapath IF FSM

Memory
Interface
Interface Mem RF
Processors Registers State State
IPs ALUs/FUs
Memories Memory Memories
ALU
Busses Gates
Custom HW
Specification System architecture Processor Implementation

+ constraints + estimates + results
• Specification to architecture to implementation

• Behavior to structure
1. System level: system specification to system architecture
2. Processor level: component behavior to component microarchitecture

System Design Needs
• Design models
• Representation for validation and analysis
• Specification for further implementation/synthesis
• Design languages
• Specification down to implementation
– Models of Computation (MoC)
• System-level design languages (SLDL)
– C-based, event-driven SLDLs [SpecC, SystemC]
 Well-defined, rigorous system-level semantics

 Unambiguous, explicit abstractions, models
– Objects and composition rules
 Systematic flow from specification to implementation
– Transformations and refinements
 Modeling flow
 Design automation for synthesis and verification
Flow
System Design Process
• Abstraction based on level of detail (structure/timing)
• Computation and communication
 System design flow
 Path from model A to model F
Cycle-
timed D F
Communication
A. System specification model

B. Component model
C. Bus-arbitration model
Approximate- D. Bus-functional model
timed C E E.Cycle-accurate computation model
F. RTL/ISS Implementation model
Un-
timed A B
Un- Approximate- Cycle- Computation
timed timed timed
Source: Lukai Cai, D. Gajski. “Transaction level modeling: An overview”, ISSS 2003
 Design methodology
 Set of models and transformations between models
Top-Down Design Flow
requirements constraints
Product planning
pure functional Specification untimed
System design
bus functional Architecture timing accurate
Processor design
RTL / IS Implementation cycle accurate
Logic design
gates gate delays
Structure Timing
© 2008 A. Gerstlauer 6
Product planning
pure functional Specification model untimed
Computation design
transaction level Computation model estimated timing
Communication design
bus functional Communication model timing accurate
Processor design
RTL / IS Implementation model cycle accurate
Structure Logic design Timing

© 2008 A. Gerstlauer 7
Product planning
Capture Algor.
IP
pure functional Specification model untimed
Computation refinement Comp.

IP
transaction level Computation model estimated timing
Communication refinement Proto.

IP
bus functional Communication model timing accurate
RTL Hardware Interface Software RTOS

IP synthesis synthesis synthesis IP
RTL / IS Implementation model cycle accurate
Structure Logic design Timing

Design Methodology
System design Validation flow
Capture
Algor.
IP
Compilation Simulation model

Specification model Validation
Analysis
Estimation
Computation refinement Comp.
IP

Computation model Validation
Analysis
Estimation
Communication refinement Proto.
IP

Communication model Validation
Analysis
Estimation
Hardware Interface Software

RTL RTOS
IP synthesis synthesis compilation IP

Implementation model Validation
Analysis
Backend Estimation

Specification Model
• High-level, abstract model

Specification model
• Pure system functionality
Computation refinement
• Algorithmic behavior
• No implementation details Computation model
• No implicit structure / architecture Communication refinement
• Behavioral hierarchy
• Untimed
Communication model
• Executes in zero (logical) time Processor refinement
• Causal ordering Implementation model
• Events only for synchronization

Specification Model Example
B1
B1
v1
B2 v2 B3
e2
• Simple, typical specification model

• Hierarchical parallel-serial composition
• Communication through ports and variables, events

Specification Level Communication
B2 v2 B3
• Message-passing e2
• Abstract communication
and synchronization
• Encapsulate in channel
B2 B3
c2

Clean Specification Model Example
B1
B1
v1
B2 B3
c2
• Synthesizable specification model

• Hierarchical parallel-serial composition
• Communication through variables and standard channels

Computation Refinement
Specification model
• PE allocation / selection
• Behavior partitioning Computation model
Communication refinement
• Variable partitioning
Communication model
• Scheduling Processor refinement
Implementation model

PE Allocation, Behavior Partitioning
B
B11
PE1 • Allocate PEs
v1 PE2 • Partition behaviors

B2 B3
c2 • Globalize communication
 Additional level of hierarchy to model PE structure

Model after Behavior Partitioning
PE1 PE2
B
B11
v1
B13snd
cb13 B13rcv
B2 B3
c2
B34rcv cb34
B34snd
 Synchronization to preserve execution order/semantics

Variable Partitioning
 Shared memory vs. message passing implementation
• Map global variables to local memories
• Communicate data over message-passing channels
B PE1 PE2
B11
v1 v1
v1
3snd B13rcv
cb13
B1
B2 B3
c2
B34rcv cb34
B34snd

Model after Variable Partitioning
B PE1 PE2
B11
v1
cb13 B13rcv
B13snd
v1
B2 B3
c2
B34rcv cb34
B34snd
 Keep local variable copies in sync

• Communicate updated values at synchronization points
• Transfer control & data over message-passing channel
Timed Computation
• Execution time of behaviors

• Estimated target delay / timing budget
• Granularity
• Behavior / function / basic-block level
 Annotate behaviors 1
behavior B2( in int v1, ISend c2 )
{
• Simulation feedback void main(void) {

5 B2_DELAY1
waitfor( delay1 ); );
• Synthesis constraints waitfor( B2_DELAY1 );
c2.send(  );

waitfor(
10 waitfor( B2_DELAY2
B2_DELAY2 );
);
}
};

Scheduling
 Serialize behavior execution on components
B
B11
PE1
• Static scheduling
– Fixed behavior execution order
– Flattened behavior hierarchy
B13snd
• Dynamic scheduling
B2
– Pool of tasks
– Scheduler, abstracted OS
B34rcv

Computation Model Example
PE1 PE2
B
B11
v1
B13snd cb13 B13rcv

v1
B2
B3
c2
B34rcv cb34 B34snd

Computation Model
• Component structure/architecture Specification model
• Top level of behavior hierarchy Computation refinement
• Behavioral/functional component view

Computation model
• Behaviors grouped under top-level
component behaviors Communication refinement
• Sequential behavior execution

Communication model
• Timed Processor refinement
• Estimated execution delays


Communication Refinement
Specification model
• Network allocation / protocol selection
• Channel partitioning Computation model
Communication refinement
• Protocol stack insertion
Communication model
• Inlining Processor refinement

Network Allocation / Channel Partitioning
PE1 PE2
B
B11
Bus1 • Allocate busses

v1
B13snd cb13 B13rcv • Partition channels

v1
B2
B3 • Update
c2 communication
B34rcv cb34 B34snd
 Additional level of hierarchy to model bus structure

Model after Channel Partitioning
PE1 PE2
B
B11
Bus1
v1 cb13 B13rcv
B13snd c2
v1
cb34
B2 B3
B34rcv B34snd

Protocol Insertion
Bus1 Bus1
cb13 Network
Protocol
c2
Layer
cb34 Layers
• Insert protocol layer

• Bus protocol channel from database
• Create network layers
• Implement message-passing over bus protocol
• Replace bus channel
• Hierarchical combination of complete protocol
stack

Model after Protocol Insertion
Master Slave
PE1 PE2
B
B11
Bus1
BusProtocol
v1 IBusMaster address[15:0]
B13rcv
IProtocolMaster
IBusSlave
IProtocolSlave
data[31:0]
B13snd ready
v1
B2 B3
B34rcv B34snd

Inlining
PE1 Bus1 PE2
BusProtocol
address[15:0]
IBusMaster
IProtocolMaster
IBusSlave
IProtocolSlave
data[31:0]
control
• Create bus interfaces

and drivers
PE1 • Refine PE2
PE1Bus communication PE2Bus
PE2Protocol
address[15:0]
IProtocolMaster
PE1Protocol
IBusMaster
IProtocolSlave
IBusSlave
data[31:0]
ready

Communication Model Example
PE1 PE2
B
B11
address[15:0]
v1 B13rcv
data[31:0]
B13snd v1
control
B2 B3
B34rcv B34snd

Communication Model
Specification model
• Component & bus structure/architecture
• Top level of hierarchy
• Bus-functional component models Computation model
• Timing-accurate bus protocols Communication refinement
• Behavioral component description

Communication model
• Timed
Processor refinement
• Estimated component delays

Processor Refinement
Specification model
• Cycle-accurate implementation of PEs Computation refinement
• Hardware synthesis down to RTL Computation model
• Software synthesis down to IS Communication refinement
• Interface synthesis down to RTL/IS

Communication model
Processor refinement

Hardware Synthesis
PE2
B13rcv
v1 PE2_CLK
PE2_CLK
Clock boundaries
B3
PE2_CLK
B34snd
• Schedule operations into clock cycles

• Define clock boundaries in leaf behavior C code
• Create FSMD model from scheduled C code

Software Synthesis
PE1
B
B11 Ff2
MOV r0,
E r1
SH r3
v1
L r2, r3,
AD r4 r2
B13snd D
IN
PUS
C r1
B2 H Ff
CAL 3
L r0
POP
B34rcv
• Implement behavior on processor instruction-set

• Code generation
• Compilation

Interface Synthesis
S0 PE1Bus PE2Bus
S1
PE2Protocol
IProtocolMaster
PE1Protocol
IBusMaster
IProtocolSlave
addr[15:0] addr[15:0]
IBusSlave
S2 data[31:0] data[31:0] DRV
ready ack ready
S3 ack
S4
• Implement communication on components

• Hardware bus interface logic
• Software bus drivers

Implementation Model
Software processor Custom hardware

PE1 PE2
OBJ
S0
Instruction PORTA address[15:0]
Set S1
Simulator PORTB data[31:0]
(ISS) S2
PORTC ready
S3
INTA ack
S4
PE1_CLK PE2_CLK

Implementation Model
• Cycle-accurate system description Specification model
• RTL description of hardware Architecture exploration
– Behavioral/structural FSMD view

Architecture model
• Object code for processors

Communication synthesis
– Instruction-set co-simulation
• Clocked bus communication Communication model
– Bus interface timing based on PE clock Processor refinement

Lecture 4: Summary
• Design methodology
• Four levels of abstraction
– Specification model: untimed, functional
– Computation model: estimated, structural
– Communication model: timed, bus-functional
– Implementation model: cycle-accurate, RTL/IS
• Three refinement steps
– Computation refinement
– Communication refinement
– Processor refinement
» HW / SW / interface synthesis
• Well-defined, formal models & transformations
– Automatic, gradual refinement
– Executable models, test bench re-use
– Simple verification

Embedded System Design Methodology

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EE382V:

Embedded System Design and Modeling

Lecture 4 – System Design Flow and Methodology

• SpecC system design methodology

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 2

Bus Control Datapath IF FSM

Specification System architecture Processor Implementation

• Specification to architecture to implementation

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 3

 Well-defined, rigorous system-level semantics

A. System specification model

pure functional Specification untimed

bus functional Architecture timing accurate

RTL / IS Implementation cycle accurate

pure functional Specification model untimed

transaction level Computation model estimated timing

bus functional Communication model timing accurate

RTL / IS Implementation model cycle accurate

Structure Logic design Timing

pure functional Specification model untimed

Computation refinement Comp.

transaction level Computation model estimated timing

Communication refinement Proto.

bus functional Communication model timing accurate

RTL Hardware Interface Software RTOS

RTL / IS Implementation model cycle accurate

Structure Logic design Timing

Compilation Simulation model

Compilation Simulation model

Compilation Simulation model

Hardware Interface Software

Compilation Simulation model

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 9

• High-level, abstract model

• No implicit structure / architecture Communication refinement

• Executes in zero (logical) time Processor refinement

• Causal ordering Implementation model

• Events only for synchronization

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 10

• Simple, typical specification model

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 11

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 12

• Synthesizable specification model

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 13

• Behavior partitioning Computation model

• Scheduling Processor refinement

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 14

v1 PE2 • Partition behaviors

 Additional level of hierarchy to model PE structure

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 15

 Synchronization to preserve execution order/semantics

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 16

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 17

 Keep local variable copies in sync

• Execution time of behaviors

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 19

 Serialize behavior execution on components

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 20

B13snd cb13 B13rcv

B34rcv cb34 B34snd

EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 21

• Component structure/architecture Specification model

• Top level of behavior hierarchy Computation refinement

• Behavioral/functional component view