VLSI Implementation Of Floating

Point Adder

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OBJECTIVE:
To design the IEEE 754/854 floating point
adder with reduced area and delay using carry
cut-back adder with better performance and
implement it in FPGA.

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INTRODUCTION:
FLOATING POINT NUMBERS:
• No fixed number of digits before and after the decimal point
• Real numbers in scientific notation have three components.

• One of the challenges in programming is that approximation

leads to reasonable results.

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FLOATING POINT ADDITION:

• Complex algorithm in which it is represented in scientific

notation as sign, exponent and mantissa.
• Before addition operation, the exponent of two floating
point numbers should be checked and normalized.
• More difficult than multiplication because alignment of
mantissa is required before mantissa addition
• To reduce Latency and area density are the main focus of
attention to improve the performance.

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 ADDERS

CLA Carry-skip Carry-save Compound CSA Parallel-prefix

ADVANTAGES

Fast •Fast No Computes Low delay oEfficient in

Reduced adder propagation both the sum compared to RCA designing
carry •Reduces delay and incremented Speed of addition oFaster in
propagation the path High clock sum. is limited by time operation
time delay speed  faster
Higher
throughput.
DIS-ADVANTAGES
Speed •Increased Don't know More area Costly oMore area
will drop complexity about the result  More area and
with of addition power
increase To implement
in bit modular
size. multiplication
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 ADDERS
APPROXIMATE ADDER

SPECULATIVE SEGMENTED CARRY SELECT APPROXIMATE FULL

ADVANTAGES

•Reduces area and Efficient design  Consumes low power Occupies reduced
power Performs faster Area efficient area and power
•Improves speed efficient

DIS-ADVANTAGES

•Moderate accuracy In- accurate error More complex Operation is slow

rate. since it is concentrated
on LSB part.

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LITERATURE SURVEY

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ADDERS TECHNIQUES ADVANTAGES DISADVANTAGES
USED
Carry save adder Early overhead is reduced  earlier calculation is
[1,3] Normalization  adder size is needed
reduced by half
 reduced latency
35%
Parallel prefix Dual reduction  eliminates  applicable for three term
Adder [13,11] complementation floating point adder
 reduces
latency[35%]
Compound adder Far and near path  speedup the  increased area[13.5%]
[4-parallel prefix + addition
carry look ahead  low latency[37%]
adder]

Compound addition  Fast rounding carry propagation

 delay of rounding is  overflow
hidden  rounding position is
changed

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Compound adder Leading One  add parallelism to  increased area[38%]
[14,20- ripple carry Predictor the design
adder + carry save  latency [6.5%]is
adder] reduced
[19- carry look ahead +
carry save adder]  improve the  more area [23%]
throughput [2.7 times]  power consumption
[28- carry look ahead Pipelining  reduced latency [5-8%]
adder + ripple carry [8.2%]
adder]
[7-parallel prefix+ high speed occupies more area
carry save adder] Conversion step can [42%]
Dual path approach be skipped
(R path and N path)  no rounding is
required
 simpler and easy to
implement

Carry look ahead Embedded shifter  enhance floating  probability of being

Adder point performance wasted space
[22]  Area[14.6%] savings
 clock rate[3.3%]
increases
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Carry look ahead Sign embedding  reduced  Carry propagation
Adder[5,7,15] latency[2.99ns]  Asymmetry of digit
set

Improve the speed  latency of alignment

 Shared exponent shift is significant
different logic  lengthy
 High performance normalization shift is
Alignment and necessary
Approximate full normalization path A small area and less In-exact adder
adder delay (31.236 ns ) produce approximate
[27] Higher performance error that can be
tolerable.

Approximate Gate level pruning Overcomes the area Approximate adder

speculative adder[26] problem that cause the
Time consumption of minimized error due to
addition process is in-exact sum that can
reduced be tolerable.
Reduces delay
[11.88%] 10
SUMMARY

• From the literature survey, Pipelining and dual path methods

occupy more area but with the significant reduction in latency.
• In early normalization and sign embedding both adder size
and latency are reduced.
• Using dual reduction latency is reduced and is applicable for
three term adder.
• Using leading one-predictor technique permits the reduction
of the delay, since it is operating in parallel with the
significand addition.
• In far and near path, exhibits the smallest latency of the three
term adders, due to elimination of a shifter from critical path.

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PROBLEMS IDENTIFIED:
• In floating point adders the problems are found as complex
exponent processing and significant alignment,
complementation after significant addition, complex round
processing,
• In order to reduce the latency, pipelining or dual path
approach can be used. But these techniques need extra
hardware and hence the area is gradually increased.
• Previously carry look ahead adder with ripple carry adders
(compound adder) are use to provide reduction in area and
better performance
• By replacing the compound adder by approximate adders
provide better performance.
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BLOCK DIAGRAM:
1 Swapping 2 Pre-normalization

IN1 Data R-shift-amt

extraction Exponent Swap Exponent Right
(S1, E1, M1) Comparator IN1, IN2 difference Shifter
IN2
(S2, E2, M2)

3 Mantissa 4 Post-normalization 5 Rounding

addition

LOP Add
(carry cut-back Left Rounding
Shifter unit Output
adder)
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FLOW CHART: Start

Enter N1 and N2 in Floating Format

Yes
Is E1/E2=0 Set S23(i.e. Hidden bit)=0 of N1 or N2
No
Yes
Is E2>E1 Swap N1 and N2

No
Calculate Difference d=E1-E2

Shift S2 of N2 to right by amount ‘d’ and fill LSB by zero’s.

Amount of shifting ‘d’ is added to the exponent of N2.

Yes N1 & N2
No
different
sign
Replace S2 of N2 by 2’s complement Yes No Compute Significant S=S1+S2

Carry out No carry out

Compute Compute
Sign=Sign of large Sign=Sign of
number N1 or N2 Previous exponent is the real exponent
Compute significant S=S1+S2
Carry out
No carry out Add ‘1’ to exponent and also shift overall result
Discard carry and shift the result to left to right dropping LSB and making MSB ‘1’
until there is ‘1’ at MSB fill LSB by zero.
MSB is ‘1’

Yes
Amount of shifting is subtracting from exponent to
Replace S by 2’s complement produce original exponent.

Assemble result into 32 bit format

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 FLOATING POINT ADDER
Exp A Exp B Mant A Mant B

Steps involved in floating Exponent difference Swap

point adder are Larger Exp

ExpB>Exp A

Exp
Pre alignment g,r,s
diff
1. Swapping
Adder
2. Pre-normalization
3. Mantissa addition Normalization

LOP
g,r,s
4. Post-normalization Shifter adjust

5. Rounding Subtract

Exponent Overflow Rounding r,s

increment unit

Exp result Mant result

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GENERAL BLOCK DIAGRAM OF CARRY CUT-
BACK ADDER DESIGN:
AN-1 –AN-X AN-2X-1 –AN-3X AX-1 –A0
BN-1 –BN-X BN-2X-1 – BN-3X BX-1 –B0

CUT CUT
PROP SPEC PROP SPEC

ADD ADD … ADD

SN-1-SN-X SN-2X-1-SN-2X SX-1-S0

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24- BIT CARRY CUT-BACK ADDER DESIGN

a, b a, b
CARRY =0 CARRY =1

CUT=0 PROP CUT=1

PROP SPEC SPEC
(1)

ADD
ADD(12 BIT) ADD(8 BIT)
(4 BIT)

S23-S12 S11-S4 S3-S0

MSB PART LSB PART

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ALGORITHM FOR CARRYCUT BACK
ADDER

prop and spec with

Cut=1 input guess
1 1 1 1
0100110010111 11011111 1111 operands

0000000000101 00000000 0100

In-exact sum

0100110011100 11011111 0011

-----------------------------------------------------------------------------------

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MANTISSA ADDITION BY APPROXIMATE
ADDER USING CARRY-CUT BACK
TECHNIQUE:
• The Approximate adder architecture called the carry-
cutback adder is used for mantissa addition.
• It includes the propagation and speculation block in which
the carry-out is ‘1’, then the propagation block cut the carry
and speculate the carry-out as ‘0’using multiplexers.
• Here the high significance carry stages are monitored to cut
the carry propagation chain at lower significance positions.
• Inexact sum cause minimized error is tolerable.

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ALGORITHM:
STEP 1: Enter N1 and N2 (operands)

STEP 2: Data extraction & Exceptional check-up

N1 S1, E1, M1 N1=2.3=0 10000000 100100100000000000000000
N2 S2, E2, M2 N2=7.4=0 10000001 111011000000000000000000
 Check for INFINITY, SUB-NORMALs, Nan (not a number)
 Update hidden bit of mantissa for sub- normal's
STEP 3,4: COMPARE, SWAP & dynamic right SHIFT:
Swap N1 & N2 E2>E1(i.e.) 10000001> 10000000

AFTER SWAPPING NEW N1 = 0 10000001 111011000000000000000000

NEW N2 = 0 10000000 100100100000000000000000
Exp difference ‘d’ {E2}-{E1} i.e., 10000001-10000000 = 00000001 (1 Bit)

Right SHIFT by ‘d’ {M2}of N2 i.e.,N2= 0 10000000 01001001000000000000000

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 d+{E2} New {E2} of N2 i.e., 00000001(1) +10000000 = 10000001

STEP 5: Pre-normalization Now E1=E2 10000001 = 10000001

STEP 6: Use Leading One Predictor (LOP)

LOP It is to Predict the no of leading ones from M1
and M2 before mantissa addition

STEP 7: Mantissa addition

1) Sign (+) calculation for the final output
2) Perform the desired operation (+)
Addition M1 + M2
(i.e.,) M1 + M2= 1 001101010000000000000000 (1 is carry )
add ‘1’ to {E} =10000010
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STEP 8: Post Normalization :
 Normalized Left SHIFT

STEP 9: Rounding
 To make sure that result after operation be fitted in to available bits.

STEP 10 : Finalizing output

 Exceptional cases Update exponent and mantissa

 Assemble S, E & M

Result is {S, E, M}= 0 10000010 001101010000000000000000

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RESULTS

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CARRY CUT-BACK ADDER RESULTS

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RTL SCHEMATIC OF CARRYCUT BACK ADDER:

25
TECHNOLOGY SCHEMATIC OF CARRY CUT BACK
ADDER:

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DEVICE UTILIZATION FOR 24 bit RCA+CLA

LOGIC USED AVAILABLE UTILIZATION

UTILIZATION
No. of Slices 23 93120 1%

No. of slice LUT 25 46560 1%

No. of occupied slices 25 11640 1%

No. of bonded IOBs 96 240 40%

DELAY 6.639 ns POWER 1.202 w

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DEVICE UTILIZATION FOR 24 BIT CLA

LOGIC UTILIZATION USED AVAILABLE UTILIZATION

No. of Slices 23 93120 1%

No. of slice LUT 34 46560 1%

No. of occupied slices 12 11640 1%

No. of bonded IOBs 74 240 30%

DELAY 6.681 ns POWER 1.293 w

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DEVICE UTILIZATION FOR 24 BIT CCBA:

LOGIC UTILIZATION USED AVAILABLE UTILIZATION

No. of Slices 23 93120 1%

No. of slice LUT 146 46560 1%

No. of occupied slices 23 146 15%

No. of bonded IOBs 73 240 30%

DELAY 1.606 ns POWER 0.042 w

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SINGLE PRECISION FLOATING POINT ADDITION
i ) swapping case (exp b> exp a)

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ii )Non-swapping case (exp a> exp b)

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iii ) Leading one prediction

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DESIGN OF FLOATING POINT ADDER
i ) with swapping case

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34
DESIGN OF FLOATING POINT ADDER
ii ) without-swapping case

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36
RTL SCHEMATIC OF FLOATING POINT ADDER:

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TECHNOLOGY SCHEMATIC OF FLOATING POINT ADDER:

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DEVICE UTILIZATION FOR FLOATING POINT
ADDER DESIGN USING CARRY CUT BACK ADDER:

LOGIC UTILIZATION USED AVAILABLE UTILIZATION

No. of Slices 886 960 92%

No. of slice flip flops 448 1920 24%

No. of 4 input slices 1589 1920 82%

No. of bonded IOBs 631 66 956%

COMBINATIONAL PATH DELAY = 11.808 ns

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DEVICE UTILIZATION FOR FLOATING POINT
ADDER DESIGN IN HIGHER ORDER FAMILIES OF
FPGA
LOGIC UTILIZATION VIRTEX 6 VIRTEX 7 ARTIX 7

No. of Slices 400/93120 (1%) 387/408000(1%) 389/126800(1%)

No. of 4 input slices 723/46560 (1%) 727/204000 (1%) 728/63400(1%)

No. of slice flip flops 292/831 (35%) 293/821 (35%) 294/823(35%)

No. of bonded IOBs 631/240 (262%) 631/600 (105%) 631/210(300%)

Minimum period (ns) 2.450 2.283 2.951

Maximum frequency 408.105 437.92 338.816

(MHZ)
Combinational path delay 0.401ns 0.395 0.396
(ns)

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 WORK TO BE DONE

PHASE II WORK:
 To perform pipelining technique in the design of
floating point adder, hence the delay can be further
reduced.

 To make the approximate adder into self-timed

adder, it helps in the reduction of delay as well as in
power. it may increase the overall performance of the
proposed IEEE-754 floating point adder design.

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CONCLUSION:

• The design of IEEE-754/854 floating point

adder is proposed using carry-cut back adder
that has the minimized latency as 1.606ns.

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THANK YOU

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