Chapter 5

Resistor Transistor Logic - RTL

Digital Electronics Dr. Bassel Soudan 1

 Resistor Transistor Logic
• The resistor Transistor Logic family is a family of
logic gates that are made exclusively of resistors
and transistors.
• The basic gate in every family is the inverter.
• The inverter is used to study the basic behavior
of the logic gates. More complex gates are
analyzed only to point out differences in
behavior.

• The basic RTL inverter is the same as the BJT

inverter we mentioned earlier.

Digital Electronics Dr. Bassel Soudan 2

 The RTL Inverter
VCC

RC

Vout

RB

• VOH = VCC Vin

• VOL = VCE (Sat)

• V IL = VBE (FA)
VCC  VCE ( Sat )
VIH  VBE ( Sat )  RB
 F RC

Digital Electronics Dr. Bassel Soudan 3

 RTL Inverter VTC
V
out

V OH = VCC

VOL = VCE (SAT)

V IL = VBE (FA) V
in
VCC  VCE ( Sat )
VIH  VBE ( Sat )  RB
 F RC

Digital Electronics Dr. Bassel Soudan 4

 The RTL NOR Gate
• An RTL NOR gate can be made by replicating
the Base resistor and the transistor in parallel for
each input
V CC

RC

V out

RB1 RB2 R BN
Q1 Q2 QN
V IN1 V IN2 V INN

Digital Electronics Dr. Bassel Soudan 5

 The RTL NOR Gate (Contd)
• Ideally, the RB for all inputs is the same and the
BJTs are matched (identical).
• In this setup, the current through RC is the sum of
all of the collector currents for the transistors:
n
I RC   I ci
  i 1

• The output voltage is

Vout = VCC - IRC * RC

Digital Electronics Dr. Bassel Soudan 6

 Operation of the RTL NOR Gate
• If all inputs are low, then all transistors are cut off
and all Ici are 0. Therefore:
n
I RC   I ci  0
i 1

Vout = VCC (VOH )

• If any input is high, then that transistor will be in

Saturation and
Vout = VCE (Sat) (VOL)

• Therefore, the circuit implements the NOR function.

Digital Electronics Dr. Bassel Soudan 7
 The RTL NAND Gate
• If the transistors are stacked instead of being in parallel, the
result is a NAND Gate:
• As in the NOR gate,
Vout = VCC- IRC * RC

• If any input is low, then that transistor will be cutoff.

Therefore, its collector current I ci = 0.
• But given that:
• Ici = Iei-1 and Ici  Iei
• Then all collector and emitter currents will be 0 and I RC = 0.
• Therefore,
Vout = VCC (VOH )

Digital Electronics Dr. Bassel Soudan 8

 VCC

The RTL NAND Gate RC

• If all inputs are high, then each of

the transistors becomes saturated Vout

and R B1
Q1

• Vout = N * VCE (Sat) (VOL)

V IN1

R B2
• Therefore, the circuit implements a V IN2
Q2

NAND gate.

• NOTE:
– Each higher transistor will require a higher input
voltage to reach saturation. This is due to the RBN
emitter of the higher transistor being connected to QN
VINN
the collector of the transistor below it. This makes
the maximum number of inputs for the RTL
NAND Gate very limited.

Digital Electronics Dr. Bassel Soudan 9

 The RTL NAND Gate Fan-in
• Fan-in
– Fan-in is the maximum number of inputs that a
gate can have and still maintain proper
functionality.

• The fan-in for an RTL NAND gate is limited by

the fact that the output low voltage VOL needs to
be low enough for a load gate to recognize it as
low.

Digital Electronics Dr. Bassel Soudan 10

 The RTL NAND Gate Fan-in (Contd)
• Consider the following VCC VCC

setup: RC RC

Vout
RB
Q
RB1
• For the RTL inverter VIN1
Q1

– VIL = VBE (FA)

•
RB2
So, for the multi-input VIN2
Q2

NAND gate to function

correctly, its output low
voltage must be smaller RBN
than VBE (FA) VINN
QN

Digital Electronics Dr. Bassel Soudan 11

 The RTL NAND Gate Fan-in (Contd)
• However, from the above circuit, we have:
• VOL = N * VCE (Sat)

• So:
N * VCE (Sat) < VBE (FA)
or

VBE ( FA )
N
VCE ( Sat )

• Assume, VCE (Sat) = 0.2 V and VBE (FA) = 0.7 V

N  0.7 / 0.2  N  3.5
– Therefore, the maximum number of inputs for an RTL NAND gate is
3

Digital Electronics Dr. Bassel Soudan 12

 V CC

V CC
R C1 RTL Fan-out
RC IRC
V out
V out R B1
Q1
RB
Q
IB1

V CC

R C2

V out
R B2
Q2

IB2

V CC

R CN

V out
R BN
QN

I BN
Digital Electronics Dr. Bassel Soudan 13
 RTL Fan-out – Output Low
• We always consider the driving gate.

• When VIN of the driver is HIGH, its Vout = VCE(Sat)

• Given that VCE (Sat) < VBE (FA)
• Then all load transistors will be cut-off
• Therefore,
IB1 = IB2 = … = IBN = 0 = IIL

• So, the low state does not affect fan-out.

Digital Electronics Dr. Bassel Soudan 14

 RTL Fan-out – Output High
• When VIN of the driver is LOW, the transistor Q is
cut-off and
Vout = VCC

• However, Vout is the VIN for each of the load

transistors.
– Therefore, Q1, Q2, …, QN will all be saturated and
taking current into their bases.
– This will cause a non-zero IRC to flow.
• and
Vout = VCC - IRC * RC
Digital Electronics Dr. Bassel Soudan 15
 RTL Fan-out – Output High (Contd.)
• Since
IRC = N * IB
• then, the more gates connected to the output the
bigger IRC becomes and the smaller Vout
becomes.
• The limit on Fan-out is when Vout drops all the
way down to VIH. At that point Q1, Q2, …, QN are
at the edge of saturation. Adding more gates will
drive the transistors out of saturation.
• Maximum Fan-out occurs when
Vout ≥ VIH
Digital Electronics Dr. Bassel Soudan 16
 RTL Fan-out – Output High (Contd.)

Vcc  Vout Vout  VBE ( Sat )

I RC  and I Bi 
RC RB

Vcc  Vout Vout  VBE ( Sat )

 N*
• IRC = N * IBi  RC RB

• Solving for N, we get

RB Vcc  Vout
N
RC Vout VBE (Sat )

Digital Electronics Dr. Bassel Soudan 17

 RTL Fan-out – Output High (Contd.)
• At maximum Fan-out, Vout = VIH.
VCC  VCE ( Sat )
VIH  VBE ( Sat )  RB
 F RC

• Substituting in the above formula we get:

Vcc  VBE ( Sat ) RB
N  F 
Vout VCE ( Sat ) RC

Digital Electronics Dr. Bassel Soudan 18

 RTL Fan-out Example
• Assume:
– VCC = 5 V, RB = 10 K, RC = 1 K, F = 25,
VBE(Sat) = 0.8 V, and VCE (Sat) = 0.2 V
 5  0.8 1K 
N  25  
 5 0.2 10 K 

• Therefore,
N = 12

Digital Electronics Dr. Bassel Soudan 19

 RTL Power Dissipation
I CC (OL)  I CC (OH )
PCC ( Avg )   VCC
2

• ICC (OL)
– For the output to be low, the
transistor must be saturated. V CC

– This makes the transistors of all I CC RC

load gates go into cut-off. The I out
V out
result would be that Iout = 0. RB +
V CE (Sat)
V in is High
-

• Then I CC (OL) 
VCC  VCE ( Sat )
RC

Digital Electronics Dr. Bassel Soudan 20

 RTL Power Dissipation (Contd)
• ICC (OH)
– For the output to be high, the
transistor must be in cut-off V CC
mode.
– That makes IC = 0. I CC RC
I out

• However, all load transistors RB

IC = 0
V
out

will be in saturation and Off

drawing current. V in is Low

– Iout = N * IB

• To simplify the calculation, we

need to come up with an
equivalent circuit for the loads.
Digital Electronics Dr. Bassel Soudan 21
 RTL Power Dissipation (Contd)
• Replacing each of the V CC

saturated load transistors RC

with a battery of value R' B

VBE(Sat), we get the VBE (Sat)

equivalent circuit on the

right. R' B

VBE (Sat)

• The circuit can further be

simplified by recognizing
that all of the RB's of the
load gates are in parallel R' B

and can be replaced by a VBE (Sat)

single RB/N.
Digital Electronics Dr. Bassel Soudan 22
 RTL Power Dissipation (Contd)
• Calculating the current, we get
VCC  VBE ( Sat )
I CC (OH ) 
R
RC  B
N

– Where N is the number of loads

Digital Electronics Dr. Bassel Soudan 23

 RTL with Active Pull-up
• To improve the fan-out of RTL gates, an active
pull-up configuration is added to the output. This
configuration increases the amount of current that
the gate can supply on its output and therefore
increases the fan-out.

• What is "active pull-up"?

V CC
• The output section of the basic RTL
inverter is made up of a simple resistor RC

(as shown on the right). V out

– This configuration produces a small,

limited amount of output current.
Digital Electronics Dr. Bassel Soudan 24
 RTL with Active Pull-up
• Keeping in mind that load gates look like
capacitors with respect to the source gate, a
large amount of current is needed to charge
these capacitors. V CC

• To increase the "sourcing" output

current, we can replace the simple R C

resistor with the "emitter follower"

combination shown on the right.
V out

Digital Electronics Dr. Bassel Soudan 25

 RTL with Active Pull-up
• The "active pull-up" increases the gate's ability to
"source" output current. This helps when the
output is high. To improve the gate's ability to
"sink" current in the low state, an "active pull-
down" combination (like the one shown below) is
also needed.

Vout

Digital Electronics Dr. Bassel Soudan 26

 RTL with Active Pull-up
• Putting the circuit together,
V CC Active Pull-Up
we get:
RC R CP

RBP
QP
V in R BS
QS

V out

RBO
QO

Active Pull-Down

Digital Electronics Dr. Bassel Soudan 27

 The RTL Inverter with Active Pull-Up
• RCP is always chosen to be much smaller then RC (about
an order of magnitude smaller). This produces a large
collector current for QP, which will produce a large emitter
current which means a large Iout.

• RBO and RBS are chosen to be equal so that QO and QS turn

on and off at the same time.

• Qs and its RBS are the simple RTL inverter from before.
The output of this combination is the inverse of the input to
the circuit. Since this output is the input of QP and the
input of the circuit is the input of QO, then QP and QO will
never be on at the same time.

Digital Electronics Dr. Bassel Soudan 28

 The inverter's operation
VIN QS QP QO Vout
HIGH Sat. Off Sat. VCE (Sat)
LOW Off F. A. Off VCC – VBE(FA) V CC

RC R CP

R BP
QP
V in R BS
QS

V out

R BO
QO

Digital Electronics Dr. Bassel Soudan 29

 Fan-out of RTL with Active Pull-Up
• Similar to the case for Basic RTL, when Vin is
high, Vout = VCE(Sat)  IIL = 0. Therefore, the high
state will determine the fan-out

• When Vin is low:

– QS is cut-off, QO is cut-off and QP is Forward
Active, the output is high.
– When this output is connected to a similar gate, QS
and QO of the load gate will be saturated and its
QP will be off.

Digital Electronics Dr. Bassel Soudan 30

 Fan-out of RTL with Active Pull-Up
– The load gate can be simplified into:
R'BS

V BE (Sat)

R'BO

V BE (Sat)

– However, since RBS and RBO are the same, we can

simplify the load gate even
R' / 2 more
B

V BE (Sat)

Digital Electronics Dr. Bassel Soudan 31

 Fan-out of RTL with Active Pull-Up
• Connecting many load R'B / 2
gates, we get the
V BE (Sat)
combination on the right.
R'B / 2

• This can be further simplified V BE (Sat)

into the circuit below:

R'B / 2N

R'B / 2
VBE (Sat)

V BE (Sat)

Digital Electronics Dr. Bassel Soudan 32

 Fan-out of RTL with Active Pull-Up
• Combining the circuit, we get:
V CC

RC RCP

RBP
F. A.

R'B / 2N
Vout
IEP N * I’IH V BE (Sat)

Digital Electronics Dr. Bassel Soudan 33

 Fan-out of RTL with Active Pull-Up
• IEP = N * I’IH
• Assuming IEP  ICP,
VCC  VCE ( Sat )  Vout Vout  V 'BE ( Sat )

RCP R'B
N

• Solving for N:
VCC  VCE ( Sat )  Vout R' B
N
Vout  V 'BE ( Sat ) 2 RCP

• Maximum fan-out occurs when Vout = VIH

• If we use typical values, we get a fan-out of about 55.

Digital Electronics Dr. Bassel Soudan 34

 Summary of RTL Discussion
• Pros:
– RTL is a very simple logic family using only a few simple
elements to make up the logic gates
– RTL has a very good high noise margin (NMH).
– The RTL Power Dissipation is acceptable.

• Cons:
– RTL has a very small low noise margin (NML).
– The RTL NAND gate suffers from a very small fan-in.
– RTL has a small and limited fan-out. This makes it not very
suitable for wide use.
– RTL utilizes a number of resistors. Resistors take a large
area on an IC to manufacture. This makes RTL non-
economical for IC manufacturing.
Digital Electronics Dr. Bassel Soudan 35