FPGA

Design
Unit-VI
1.FPGA Architecture
 Figure below illustrates the basic architecture
of an FPGA. The architecture encompasses three
types of configurable elements. They are,
A core array of logic blocks
Input-output blocks
Switch blocks.
The input-output block and the switched
block are collectively known as routing resources.
The digital circuit implemented on FPGA by
configuring the logic block and the routing
resources.
Figure: Basic FPGA Architecture
 The digital circuit to be implanted on
the FPGA is disintegrated into smaller sub-
circuits so that each element can be
mapped on to a logic block in the FPGA.
The essential connectivity between
the sub-circuits is realized using the routing
channels.
The horizontal and vertical lines in
the FPGA architecture called tracks denote
the routing channel resources.
 The input-output blocks offer a
programmable interface between the internal
array of logic blocks and the FPGAs external
package pins.
Logic blocks can carry-out
combinational and sequential logic functions
specified by the user.
The switch block connects the horizontal
and vertical routing channels.
2. FPGA CONFIGURATION
 Due to the volatile nature of FPGAS
the contents on it gets reused, when the
systems power is turned off or
interrupted. So the FPGA does not store
the program on itself.
Whenever you want to use FPGA, it
is essential to Upload a program to it.
Therefore, a configuration element must
be used with the FPGA.
Configuration Element:
FPGA can be configurable by using one of these
configurations below:
Computer : it is used for quick and easy program
development. The computer usually is not needed after
the design completed. Therefore it is used at the stage of
program development. The cables given with the
development boards are used for this purpose.
Microcontroller : A microcontroller which has an
embedded program can be used to configure the FPGA.
Boot-PROM : These are FPGA manufacture own Boot-
PROMs. They are used to configure the FPGA
automatically after turning power ON.
 During the programming of
FPGA, Two types of PROM’s
are used. They are,

1. One Time programmable (OTP) ROM

2. In system programmable (ISP) ROM

 The steps involved in configuration
the FPGA are,
Step 1: Using VHDL or verilog code, a design entry process is
done. This creates an EDIF (Electronic Design Interchange
Format) net file.
Step 2: The created file is loaded on to a particular FPGA or
CPLD and extension files is generated. The generated
extension file is also called as bit stream file.
Based on the devices used, the different forms of
extension files generated are,
FPGA .bit
CPLD .jed
PROM .mcs, exo, .tek
Step 3: Finally, an FPGA is configured using software like
Xilinx ISE (integrated software environment).
Figure: configuring the FPGA

VHDL verilog Design entry

Net list (EDIF)

Implementation For a specific Device

Bit stream (bit) the PROM file

Configure the FPGA program The PROM

3.Different Modes used for
Configuration of FPGA
1.JTAG Mode
2.Master –serial Mode
3.Slave-Serial Mode
4.Slave-parallel Mode
1.JTAG Mode : (Boundary Scan Mode)
It is a serial programming mode used to program
devices like FPGA, CPLD and PROM, A JTAG cable is
used to load the configuration of data at the rate of one
bit per test clock tick.
2. Master –serial Mode :
It is a serial mode used to load the data from
PROM to FPGA. An internal oscillator in the FPGA is
used to generate a clock pulse and to load the data at the
rate of one bit per test clock tick.
3. Slave-Serial Mode : An external clock pulse from a

microprocessor or another FPGA is used to load the data

into FPGA at the rate of one bit per test clock.

4.Slave-parallel Mode : It is similar to that of slave serial

mode but the only difference is that data is transferred in
bytes instead of bits. Hence the configuration speed (data
transfer rate) is fast.

The most commonly used modes are JTAG and

master-slave.
4.FPGA Design process
 Tools in FPGA
The major tool used in the configuration of
FPGA is CAD (computer Aided Design).

The other tools used are

1. Model simulator
2. Quarter software
3. Integrated Software Environment (ISE).
 FPGA Design Flow
(The steps involved in designing an FPGA)
1.Specifications : System requirements such as
number of input and output, number of gates, macro
cells required to design an FPGA are specified.
2.Implementation in HDL : using VHDL editor or
graphical editor, design entry process is done to
implement block diagram and to generate HDL
code.
3.Functional or Behavioral Simulation : The
simulator used in FPGA explains the HDL code and
then it sets the break point and traces the function
and procedure. Thus, it helps in understanding the
system design process.
4.Synthesis : The synthesis block converts generated
HDL code into list.
5.Net list : it is used to represent the actual circuit
diagram with the help of adders, multiplexers etc.
6.Post Synthesis Simulation : The post simulator
compares the present state result with the
behavioral synthesis result. If the results are
different then it checks the errors and corrects
them.
7.Mapping, Placing and Routing: It maps the net
list file into bit stream file and establishes a critical
path to the target device FPGA to meet the timing
constraints during implementation process.
8.Bit Stream : The bit stream file generates bit
extension for FPGA.
9.Timing Simulation : In timing simulation, test
bench waveforms are to verify whether the timing
constraints of target device FPGA are met or not.
 5. The vendors of FPGA family
Actel
Atmel
Altera
Xilinx
Lattice semiconductor
 The Factors considered in selecting a vendor are

• The vendor should have a development (or)

evaluation board to design any specific prototype.
• The vendor should be able to present the different
designs of development board.
• The preference should be given to those vendors
who suggest the choice in selecting an FPGA by
providing supporting tools.
6.Implementation of STACK
using VHDL code
 A STACK is a data structure which
operates with first in first out logic. i.e.
the data entered first leaves the stack at
last. When stack is full, data cannot be
further loaded into it.
Similarly when Queue is empty, data
cannot be removed from it.
Practically a Stack can be
implemented with the help of DPRAM
(Dual port Random Access Memory).
 stack has 6 input ports and 3 out ports
Input ports:-
CLK : Clock
CS : Chip Select
Rd : Read
RST : Reset
WR : Write
Input Data : Data input to stack
Output ports:-
Full : During the write operation, when all the memory
locations are full, then the signals is active high.
Empty : when all the memory, locations are empty, then the
signals is active high.
Output : Output Data.
VHDL implementation of the stack
Library declaration library ieee;
Use ieee.numeric-std.all;
Use ieee.std-logic-1164.all;
Use ieee.std-logic-arith.all;
Use ieee.std-logic-unsigned.all;
--input ports
wr : in std-logic; -- write enable

Rd : in std-logic; --read enable

Clk : in std-logic; --clock

Rst : in std-logic; --reset

Cs : in std-logic; --Chip Select

Data in : in-std-logic-vector;
-- output ports

Empty : out std-logic ; ----high when stack is empty

Full : out std-logic ; ---high when stack is full

Data out : out std-logic-vector;

End stack;
7.Explain implementation of
QUEUE using VHDL code
 A queue is a data structure
which operates with first in first
out logic. i.e; the data entered
initially leaves first from the
queue.
When queue is full, data
cannot be further loaded into it.
Similarly when queue is empty,
data cannot be removed from it.
 Queue has 6 input ports and 5
out ports.
The input ports are :
CLK : clock
CS : chip select
RD : Read
RST : Reset
WR : Write
Input data : Data input to queue
The out put ports are :
Full : During the write operation, when all the
memory locations are full, then the signal is active
high.
Empty : when all the memory locations are empty,
then the signal is active high.
Almost full : During the write operation, when all
the memory locations are full,except one memory
location then the signal is active high.
Almost empty : during the read operation, when all
the memory locations are full, except one memory
location then the signal is active high.
Output : data output.
VHDL implementation of the queue:-

--- LIBRARY DECLARATION

LIBRARY IEEE;
USE IEEE STD-LOGIC-1164.ALL;
USE IEEE.STD-LOGIC-UNSIGNED.ALL;
USE IEEE.STD-LOGIC-ARITH.ALL;
INPUT PORTS
clk : in std-logic ; -----CLOCK
Rst : in std-logic ; -----RESET
Cs : in std-logic ; -----CHIP SELECT
Wr : in std-logic ; ------WRITE ENABLE
Rd : in std-logic ; -----READ ENABLE
Input data : in out std-logic;
OUTPUT PORTS
Almost full : out std-logic ;
Almost empty : out std-logic ;
Empty : out std-logic ;
Full : out std-logic ;
Output : out std-logic-vector;
End Queue :
 HOME WORK

8. FPGA DESIGN EXAMPLE SHIFT REGISTER

IMPLEMENTATION USING VHDL.

9. STEP-BY-STEP APPROACH OF FPGA DESIGN

PROCESS ON XILINX ENVIROMENT.