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FET

(FIELD EFFECT
TRANSISTOR)
FET’S VS. BJT’S

Similarities:
Amplifiers
Switching Device
Impedance Matching Circuits
DIFFERENCES

FET’s BJT’s
 Voltage controlled  Current controlled devices
devices  Lower impedance
 Higher input impedance  Higher sensitive
 Less sensitive to temp.  Bipolar device
variations  Bigger IC
 Unipolar device

 Smaller/ Easily
Integrated Chips
TYPES OF FET

1. JFET (Junction FET)


2. MESFET (metal-semiconductor FET)
3. MOSFET (metal-oxide-semiconductor
FET)
1. D-MOSFET (Depletion)
2. E-MOSFET (Enhancement)
DR. IAN MUNRO ROSS
&
G.C DACEY

- Jointly developed an experimental


procedure for measuring the
characteristics of FET in 1955
JFET
(JUNCTION FET)
CONSTRUCTION AND CHARACTERISTICS OF
JFET
 Is a three-terminal device with one terminal capable
of controlling the current between the other two.

3 terminals are:

• DRAIN (D)
• SOURCE (S) – connected to n-channel
• GATE (G) – connected to p-channel
Two types of JFET
1. n-channel
2. p-channel
Drain Drain

Gate Gate

Note: Source Source

 n-channel is more widely used.


D D

G G

S S
n-channel p-channel
Water Analogy for the JFET control mechanisms
JFET OPERATING
CHARACTERISTICS
 JFET is always operated with the gate-source PN
junction reversed biased.

 Reverse biasing of the gate source junction with the


negative voltage produces a depletion region along the
PN junction which extends into the n-channel and thus
increases its resistance by restricting the channel width
as shown in the preceding figure.
�𝑮𝑺 = ૙, �𝑫𝑺 SOME POSITIVE VALUE
When �𝐆𝐒 = ૙ 𝐚𝐧𝐝 �𝐃𝐒 is increased from
0 to a more positive voltage.

The depletion region between p-gate


and n-channel increases

Increasing the depletion region,


decreases the size of the n-channel
which increases the resistance of the n-
channel.

 Even though the n-channel resistance


is increasing, the current (ID) from
source to drain through the n-channel
is increasing. This is because VDS is
IG = increasing.
Ͳ
Recall from DIODE discussion:
- The greater the applied reverse bias, the wider is the depletion region.
REGIONS OF JFET ACTION
1. Ohmic Region – linear region
1. JFET behaves like an ordinary resistor
2. Pinch Off Region
 Saturation or Amplifier Region
 JFET operates as a constant current device because
Id is relatively independent of Vds

 Idss – drain current with gate shorted to source.


• Breakdown Region
If Vds is increased beyond its value corresponding to Va
– avalanche breakdown voltage.
1. JFET enters the breakdown region where Id increases to
an excessive value.
4. Cut Off Region
 As Vgs is made more and more negative, the gate
reverse bias increases which increases the
thickness of the depletion region.
4. As negative value of Vgs is increased, a stage
comes when the 2 depletion regions touch each other.

Vgs (off) = -Vp


/Vp/ = /Vgsoff/
JFET OPERATING CHARACTERISTICS: PINCH OFF

 If VGS = Ͳ and VDS is further


increased to a more positive
voltage, then the depletion zone
gets so large that it pinches off the
n-channel.

 As VDS is increased beyond |VP |,


the level of ID remains the same
(ID= IDSS)
�𝑮𝑺 ૙ ૙
Voltage from gate to source is controlling
voltage of the JFET.

As �𝐆𝐒 becomes more negative, the


depletion region increases.

The more negative �𝐆𝐒, the


resulting level for �𝐃 is reduced.

Eventually, when �𝐆𝐒 = �𝐩 [Vp = VGS


(off)], ID is 0 mA. (the device is
“turned off”.
JFET OPERATING CHARACTERISTICS

n-Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.


JFET OPERATING CHARACTERISTICS: VOLTAGE-
CONTROLLED RESISTOR
The region to the left of the
pinch-off point is called the
ohmic region/Voltage controlled
resistance region.

The JFET can be used as a variable resistor, where VGS controls the drain-
source resistance (rd). As VGS becomes more negative, the resistance (rd)
increases
where ro is the resistance with VGS=0 and rd is the
resistance at a particular level of VGS.
FOR EXAMPLE:
1. For an n-channel JFET with �૙ = ͳͲ݇Ω �૙૙૙
ௌௌ =

ͳͲ݇Ω
�𝑑 =
−͵
ሺͳ −૙
− ሻଶ

�𝑑 = ͶͲ݇Ω
P-CHANNEL JFETS

The p-channel
JFET behaves the same
as the n-channel JFET,
except the polarities
voltage and
current directions are
reversed.
P-CHANNEL JFET CHARACTERISTICS

Also note that at high levels of VDS


the JFET reaches a breakdown
situation: ID increases uncontrollably
if VDS > VDSmax
JFET SYMBOLS

JFET symbols: (a) n-channel; (b) p-channel.


SUMMARY:
Important parameters to remember:

VGS = ͲV, ID = IDSS

Cutoff (�૙ = Ͳ�)


�૙૙૙
ௌௌ less than the
pinch off level
�૙ is between 0 A and �૙૙૙ ௌௌௌௌ݂૙� �ௌௌ ૙
�݊
Ͳ� ���ℎ�
�� ݊ � ��
�ℎℎ
�� �ℎ� �ℎ �݊ℎ ૙݊ܿ�ℎ .
JFET TRANSFER CHARACTERISTICS

In a BJT, 𝛽 indicates the relationship between �૙ (input) and �૙ (output).


Control variable

�૙ = ݂ �૙ = 𝛽�૙

Constant

In a JFET, the relationship of �૙૙૙


ௌௌ (input) and �૙ (output) is defined by
Shockley’s Equation
Control variable

ͳ − �૙
�૙ = �૙
૙૙
ௌௌ
�ௌௌௌௌ
૙૙
Constant
Co-inventor of the first
transistor and formulator of
the “field effect” theory
employed in the
development of the
transistor and the FET

William Bradford Shockley


(1910–1989)
This graph shows the value of �𝑫 for a given value of �𝑮𝑺.
PLOTTING THE JFET TRANSFER CURVE
Using �૙૙૙
ௌௌௌௌ and �૙ (�૙૙૙ ݂
ௌௌሺ૙૙૙ ሻ) values found in a specification sheet, the
transfer curve can be plotted according to these three steps:

Step 1:

Solving for �૙ௌௌ = �૙ ,
�૙ = ͳ − ૙૙ ID = IDSS
�૙
ௌௌ
Ͳ,
Step 2: �ௌௌௌௌ
૙૙

Solving for �૙ௌௌ = ݂૙૙૙ �૙ௌௌ
ௌௌ ID = Ͳ A
�૙ = ͳ− ,
�૙(�૙ௌௌ
ௌௌ
), �૙
�ௌௌௌௌ
Step 3:

Solving for �૙ if we substitute �૙ௌௌ = −ͳ � , �ௌௌௌௌ = 8mA and �૙ =-4



ሺ−
ௌௌଶ
�૙ௌௌ
, ݉
�૙ = ͺ� ,
�૙ = ͳ− ͳ−
�૙ ͳሻ
�ௌௌௌௌ ID = Ͷ.ͷmA ሺ−Ͷሻ
Conversely, for a given Shorthand
�૙ , �૙૙૙
ௌௌ can be
obtained: Method:
ଶ �૙ �૙
ͳ − �૙ �૙ = �૙ =
�૙ = �૙
૙૙
ௌௌ Ͷ
ௌௌ
૙૙
ௌௌ ʹ
�ௌௌௌௌ ௌௌ

�૙
�૙ௌௌ = �૙ ͳ �૙
�૙ �૙૙૙
ௌௌ ≅ Ͳ.͵�૙ �૙
− ௌௌ ʹ
ௌௌ
ௌௌ = ௌௌ
For Example:
Sketch the transfer curve defined by �૙૙૙ ݉ and �૙ = −૙�.
ௌௌௌௌ = ͳʹ�

By shorthand method,

@ �
�૙૙૙ −૙ = −૙�
ௌௌ =૙ = ʹ
ʹ

�૙ = �𝐷𝑆𝑆

= ଵଶ૙஺ = ૙𝒎�

@
�૙ = �૙ = ͳʹ�
݉ = ૙𝒎�
ʹ
ௌௌʹ
ௌௌ

�૙૙૙
ௌௌ ≅ Ͳ.͵�૙ = Ͳ.͵ = −૙.
−૙� ૡ�
IMPORTANT RELATIONSHIPS
MOSFET
(METAL-OXIDE-
SEMICONDUCT
OR FET)
THERE ARE TWO TYPES OF MOSFETS:

 Depletion-Type
 Enhancement-Type
DEPLETION-TYPE MOSFET CONSTRUCTION
 The Drain (D) and Source (S)
connect to the to n-doped regions.

 These n-doped regions are


connected via an n-channel.

 This n-channel is connected to the


Gate (G) via a thin insulating layer
of SiO2.

 The n-doped material lies on a p-


n-Channel depletion-type doped substrate that may have an
MOSFET additional terminal connection
called Substrate (SS).
Dielectric
insulator
SILICON DIOXIDE:
 Insulator refer to as DIELECTRIC.
 It sets up opposing electric field within the dielectric
when exposed to an externally applied field.
 The fact that SiO2 layer is an insulating layer
means that:

There is no direct electrical connection between


the
gate terminal and the channel of a MOSFET.
It is the insulating layer of SiO2 in the MOSFET
construction that accounts for the very desirable high
input impedance of the device
WHY MOSFET?
 Metal:
 For the drain, source, and gate connection for the proper
surface – in particular, the gate terminal and the control to be
offered by the surface area of the contact.
 Oxide:
 For the Silicon dioxide insulating layer.
 Semiconductor:
 For the basic structure on which the n- and p-type region are
DIFFUSED.

MOSFET is also called INSULATED


GATE-FET or IGFET
DEPLETION-TYPE MOSFET :BASIC OPERATION
AND CHARACTERISTICS

 VGS = Ͳ and VDS is applied


across the drain to source
terminals.

 This results to attraction of


free electrons of the n-
channel to the drain, and
hence current flows.
Continuation….
 is set at a negative
�૙૙૙ௌvoltage
ௌ such as -1 V
The negative potential at
gate
the pressure electrons
toward the p-type substrate
and attract the holes for
the
p-type substrate.
This will reduce the
number of free electrons
in the n- channel
available for conduction.
The more negative the
�૙ௌௌ , the resulting level of
drain current �૙ is reduced.
When �૙ௌௌ is reduced
to �𝑃 (pinch off voltage),
then �૙ = Ͳ� ݉ .
݉ .
When �૙ௌௌ is reduced to �𝑃 (pinch off) {i.e �𝑃 = −૙�} then �૙ = Ͳ�

For positive values of �૙ௌௌ


ௌௌ, the positive gate will draw additional
electrons (free carriers from the p-type substarte and hence �૙
increases.)
DEPLETION-TYPE MOSFET CAN OPERATE IN TWO
MODES:

 Depletion mode
 Enhancement mode
D-TYPE MOSFET IN DEPLETION MODE

The characteristics are similar to a JFET.

 When �૙૙૙ௌௌ = Ͳ�, �૙ = �ௌௌௌௌ


૙૙
 When �૙૙૙ௌௌ < Ͳ�, �૙ < �ௌௌௌௌ


ͳ − �૙
�૙ = �૙
૙૙
ௌௌ
�ௌௌௌௌ
૙૙
D-TYPE MOSFET IN ENHANCEMENT MODE

@ �૙ௌௌ > Ͳ
�૙ increase above the
�ௌௌௌௌ

ͳ − �૙ௌௌ
ௌௌ
�૙ = �૙
�ௌௌௌௌ
Note:
�૙૙૙
ௌௌ is now positive
D-TYPE MOSFET SYMBOLS
ENHANCEMENT-TYPE
MOSFET
ENHANCEMENT-TYPE MOSFET CONSTRUCTION

 The Drain (D) and Source (S)


connect to the to n-doped
regions.

 The Gate (G) connects to the


p-doped substrate via a thin
insulating layer of SiO2

 There is no channel

 The n-doped material lies


on a p-doped substrate that
may have an additional
terminal connection
 For �૙ௌௌ = Ͳ, �૙ = Ͳ(no
 For �ௌௌ some positive voltage
channel)
and �૙ௌௌ = 0, two reversed
biased n-junctions and no
significant flow between drain
and source.

 For �૙ௌௌ > Ͳ and �૙ௌௌ > Ͳ, the


positive voltage at gate pressure
holes to enter deeper regions of
the p-substrate, and the electrons
in p-substrate and the electrons
in p-substrate will be attracted to
the positive gate.
The level of �૙ௌௌ that results in
the significant increase in drain
current in called:
THRESHOLD VOLTAGE (Vt)
 For �૙ௌௌ < ૙், �૙ = Ͳ� ݉
BASIC OPERATION OF THE EN-oTteY:PE MOSFET
The enhancement-type MOSFET
operates only in the enhancement
mode

�૙૙૙
ௌௌ is always positive

As �૙ௌௌ increases, �૙ increases


As �૙ௌௌ is kept constant and �ௌௌ is
increased, then �૙ saturates (�ௌௌௌௌ )
and the saturation level, �૙૙ ௌௌௌ
૙ௌௌ ௦ ௧
is reached.
�૙૙ ૙ௌௌ ௦
ௌௌௌ can
௧ be calculated by

�૙௦૙૙௧ = �૙૙૙
ௌௌ − �்
E-TYPE MOSFET TRANSFER CURVE

To determine �૙ given �૙૙૙ௌௌ: Where,


૙૙் is the threshold voltage or voltage at which the MOSFET turns on.
݇݇, a constant, can be determined by using values at a specific point and the
formula:
FOR EXAMPLE:
݉ ‫ݓ‬ℎ݊� ��ௌௌௌሺ૙૙૙ሻ =
Substituting �૙ሺ૙૙૙ሻ = ͳͲ�
ͺ�

The level of ૙૙் is 2V, as revealed


by the fact that the drain current has
dropped to 0 mA.

݉
ͳͲ�
݇ =
݇
ሺͺ� − ʹ�ሻଶ
�૙૙−૙ �
= ૙. ૙ૠ ૡ
�૙
Note:
For values of �૙૙૙ௌௌ less than the threshold level, the drain current of an
enhancement type MOSFET is 0 mA.

Substituting the �૙ௌௌ from the general equation:

�૙ = ݇ሺ��ௌௌௌ − �் ሻଶ
݇ = Ͳ.ʹ૙ͺ‫Ͳͳݔ‬−ଷ
݇

݉ /�ଶሺ�ௌௌ
�૙ = Ͳ.ʹ૙ͺ� − ʹ�ሻଶ

i.e substituting �૙ௌௌ = Ͷ�, we find that

݉ /�ଶሺͶ� − ʹ�ሻଶ
�૙ = Ͳ.ʹ૙ͺ�
�𝑫 = ૙. ૙૙𝒎�
MOSFET SYMBOLS
VMOS
VERTICAL MOSFETS
VMOS CHARACTERISTICS:
 Compared with commercially available planar
MOSFETs, VMOS FETs have reduced channel
resistance levels and higher current and power
ratings
 VMOS FETs have a positive temperature
coefficient that will combat the possibility of
thermal runaway
The reduced charge storage levels result in faster
switching times for VMOS construction
compared to those for conventional planar
construction
CMOS
COMPLEMENTARY MOSFETS
CMOS CHARACTERISTICS:

Extensive application in computer logic


design
Relatively high input impedance
Fast switching speeds
Lower operating power levels – CMOS
logic design
MESFETS
Metal semiconductor FETs
ASSIGNMENT:
1.In what ways is the construction of a depletion type
of MOSFET similar to that of a JFET? In what ways is
it different?

2.What is the significant difference between the


construction of an enhancement type MOSFET and a
depletion type MOSFET?

3. Sketch the transfer characteristics of a p-channel


enhancement type MOSFET if ૙૙் −ͷ� and ݇ =
Ͳ.Ͷͷ‫Ͳͳݔ‬−ଷ � =
�ଶ.
SOURCE:
Electronic Devices and Circuit Theory, 10th Ed., R.
Boylestad & L. Nashelsky, Copyright ©2009 by
PEARSON Education, Inc.
FET
Biasing
Basic Current Relationships

Things to ponder!
Fixed-Bias Configuration

�𝑮 ≅ 𝟎�

૙૙ோோ� = �𝐺 �𝐺 = 0 = �𝐺 0�

The zero volt across �𝐺


drop permits by a
replacing �𝐺 circuit short
equivalent.
@ loop 1:

−�𝐺𝐺 − �૙૙૙
ௌௌ = 0

�𝑮૙ = −�𝑮𝑮
2

@ loop 2:
1 �𝐷𝐷 − �𝐷�𝐷 − �૙૙૙
ௌௌ − �ௌௌ =
0
૙૙ௌௌ = �𝑫૙ = �𝑫𝑫 − �𝑫૙𝑫
0

Using Double subscript notation:

�૙૙૙
ௌௌ = �𝐷 �૙૙૙
ௌௌ = �𝐺
− �� − ��
� =�
For
Example: Find:
Self-Bias Configuration
@ loop 1:

−�૙ௌௌ − �ோோ� = 0
�𝑮૙ = −�૙𝒔 = −�𝐷 ��

૙૙ோோ� = �𝐷
��

Note that the


current through
�� is the
source current,
૙૙ௌௌ
But
�𝐷 = �𝐷𝐷 −
૙૙ோோ𝐷
Self-Bias Configuration –
graphical solution
1. Sketch the transfer curve
2. Draw the line
�𝑮૙= −�𝐷 ��
1. The Q-point is located where the
line intersects the transfer curve.

Shorthand
Method:

�૙ �
�𝐷 = ௌௌௌௌ
૙૙૙ �૙૙૙
ௌௌ =�
Voltage-Divider Bias
Using voltage divider, you get the
value of �
For Example:
Source:
Electronic Devices and Circuit
Theory, 10th Ed., R. Boylestad &
L. Nashelsky, Copyright ©2009
by PEARSON Education, Inc.