Lecture 23 – Digital Electronics

RIJIL RAMCHAND
 MOSFET Digital Circuits
 Analyze and design NMOS inverters
 Analyze and design NMOS logic gates
 Analyze and design CMOS inverters
 Analyze and design static CMOS logic gates

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 NMOS inverters
 The inverter is the basic circuit of most MOS logic
circuits.
 The design techniques used in NMOS logic circuits are
developed from the dc analysis results for the NMOS
inverter.
 Extending the concepts developed from the inverter to
NOR and NAND gates is then direct.
 Alternative inverter load elements are compared in terms
of power consumption, packing density, and transfer
characteristics.

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NMOS Inverter Transfer Characteristics

 Since the inverter is the basis for most logic circuits, we

will describe the NMOS inverter and will develop the dc
transfer characteristics for three types of inverters with
different load devices.
 We will introduce voltage transfer functions and will
define the maximum and minimum logic levels.

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 NMOS Inverter with Resistor Load
a

 Figure (a) shows a single

NMOS transistor connected
to a resistor to form an
inverter.
 The transistor characteristics
and load line are shown in
b Figure (b), along with the
parametric curve separating
the saturation and
nonsaturation regions.

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 NMOS Inverter with Resistor Load
a
 When the input voltage is less
than or equal to the threshold
voltage, or vI ≤ VT N , the
transistor is cut off, iD = 0, and
the output voltage is vO = VDD.

 The maximum output voltage is

defined as the logic 1 level.
b
 As the input voltage becomes
just greater than VTN, the
transistor turns on and is
biased in the saturation region.

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 NMOS Inverter with Resistor Load
a  The output voltage is then

 which relates the output and input

voltages as long as the transistor is
b biased in the saturation region.

 As the input voltage increases, the Q-

point of the transistor moves up the
loadline. At the transition point, we have

 where VOt and VIt are the drain-to-source

and gate-to-source voltages,
respectively, at the transition point.
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 NMOS Inverter with Resistor Load
a
 We determine the input voltage at the
transition point from

 As the input voltage becomes greater

than VIt, the Q-point continues to move
up the load line, and the transistor
becomes biased in the nonsaturation
region. The drain current is then
b

 which relates the input and output

voltages as long as the transistor is
biased in the nonsaturation region.

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 NMOS Inverter with Resistor Load
 Figure shows the voltage transfer
characteristics of this inverter for three
resistor values.

 Also shown is the line, given by Equation

 which separates the saturation and

nonsaturation bias regions of the transistor.

 The figure shows that

the minimum output voltage, or the logic

0 level, for a high input decreases with
increasing load resistance.
Voltage transfer characteristics of NMOS
the sharpness of the transition region
inverter with resistive load
between a low input and a high input
increases with increasing load
resistance.
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 NMOS Inverter with Resistor Load

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 NMOS Inverter with Resistor Load
It should be noted that a large resistance is difficult to
fabricate in an IC.

A large resistor value in the inverter will limit current

and power consumption as well as provide a small VOL
value.

But it would also require a large chip area if fabricated

in a standard MOS process.

To avoid this problem MOS transistors can be used as

load devices, replacing the resistor, as discussed in
coming slides.

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 NMOS Inverter with saturated load

 An n-channel enhancement-mode MOSFET with the

gate connected to the drain can be used as a load
device in an NMOS inverter.
 The analysis of this configuration shows that, when vGS =
vDS ≥ VTN , the transistor always operates in the
saturation region.

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 NMOS Inverter with saturated load
 Figure shows an NMOS inverter with the
enhancement load device.
 The driver transistor parameters are
denoted by VTND and KD, and
 the load transistor parameters are
denoted by VTNL and KL
 The substrate connections are not
shown.
 In the following analysis, we neglect the
body effect and we assume all threshold
voltages are constant.
 These assumptions do not seriously
affect the basic analysis, nor the inverter
characteristics.
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 NMOS Inverter with saturated load

 The driver transistor characteristics

and the load curve are shown in
Figure (b).

 When the inverter input voltage is

less than the driver threshold
voltage, the driver is cut off and the
drain currents are zero.

 From Figure (a), we see that vDSL =

VDD − vO , which means that

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 NMOS Inverter with saturated load
 For the enhancement-load NMOS
inverter, the maximum output
voltage, which is the logic 1 level,
does not reach the full VDD value.
This cutoff point is shown in the load
curve in Figure (b).
 As the input voltage becomes just
greater than the driver threshold
voltage VTND, the driver transistor
turns on and is biased in the
saturation region.
 In steady-state, the two drain
currents are equal since the output
will be connected to the gates of
other MOS transistors.

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 NMOS Inverter with saturated load

 We have iDD = iDL, which can be

written as

 In terms of the input and output

voltages, the expression becomes

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 NMOS Inverter with saturated load

Voltage transfer characteristics of NMOS

inverter with saturated load
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 NMOS Inverter with Depletion Load

current–voltage characteristic of depletion load

NMOS inverter with depletion load

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driver transistor characteristics and load curve
 NMOS Inverter with Depletion Load

Voltage transfer characteristics of an NMOS inverter

with depletion load

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 NMOS logic circuits

 NMOS logic circuits are formed by combining

driver transistors in parallel, series, or series–
parallel combinations to produce a desired
output logic function.

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 NMOS NOR and NAND Gates

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 NMOS NOR and NAND Gates

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 CMOS inverter
 Complementary MOS, or CMOS, circuits contain
both n-channel and p-channel MOSFETs.
 As we will see, the power dissipation in CMOS
logic circuits is much smaller than in NMOS
circuits, which makes CMOS very attractive.
 We will analyze the CMOS inverter, which is the
basis of most CMOS logic circuits.
 We will examine the CMOS NOR and NAND
gates and other basic CMOS logic circuits.
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 CMOS inverter
 The CMOS inverter, shown in
Figure 16.21, is a series
combination of a p-channel and
an n-channel MOSFET.
 The gates of the two MOSFETs
are connected together to form
the input and the two drains are
connected together to form the
output.
 Both transistors are
enhancement-mode devices.
 The parameters of the NMOS
are denoted by Kn and VTN,
where VTN > 0, and the
parameters of the PMOS are
denoted by Kp and VTP, where
VTP < 0.
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 CMOS inverter

 Figure 16.22 shows a simplified cross section of a CMOS inverter.

 In this process, a separate p-well region is formed within the starting n-
substrate.
 The n-channel device is fabricated in the p-well region and the p-channel
device is fabricated in the n-substrate.
 Although other approaches, such as an n-well in a p-substrate, are also used
to fabricate CMOS circuits, the important point is that the processing is more
complicated for CMOS circuits than for NMOS circuits.
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 CMOS inverter

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 CMOS inverter

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 CMOS logic circuits
 Large-scale integrated CMOS circuits are used
extensively in digital systems, including watches,
calculators, and microprocessors.
 We will look at the basic CMOS NOR and NAND
gates, and will then analyze more complex CMOS
logic circuits.
 Since there is no clock signal applied to these logic
circuits, they are referred to as static CMOS logic
circuits.

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Basic CMOS NOR and NAND Gates

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Basic CMOS NOR and NAND Gates

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