Beruflich Dokumente
Kultur Dokumente
Microprocessors and
Microcontrollers
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech , Erode
Microprocessor
• Microprocessor (µP) is the “brain” of a computer that
has been implemented on one semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
To process means to manipulate. It describes all
manipulation.
Micro - > extremely small
2
Definition of a Microprocessor.
The microprocessor is a programmable
device that takes in numbers, performs on
them arithmetic or logical operations
according to the program stored in memory
and then produces other numbers as a result.
3
Microprocessor ?
A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
4
Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems
5
MICROPROCESSOR HISTORY
6
DIFFERENT PROCESSORS AVAILABLE
Socket
Pinless
Processor
Processor Slot
Processor
ProcessorSl
ot
7
Development of Intel Microprocessors
• 8086 - 1979
• 286 - 1982
• 386 - 1985
• 486 - 1989
• Pentium - 1993
• Pentium Pro - 1995
• Pentium MMX -1997
• Pentium II - 1997
• Pentium II Celeron - 1998
• Pentium II Zeon - 1998
• Pentium III - 1999
• Pentium III Zeon - 1999
• Pentium IV - 2000
• Pentium IV Zeon - 2001
8
GENERATION OF PROCESSORS
Processor Bits Speed
8080 8 2 MHz
8086 16 4.5 – 10
MHz
8088 16 4.5 – 10
MHz
80286 16 10 – 20
MHz
80386 32 20 – 40
MHz
80486 32 40 – 133
MHz
9
GENERATION OF PROCESSORS
12
8-bit Microprocessors
13
Intel 8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
14
Intel 8080
Introduced in 1974.
It was also 8-bit µP.
Its clock speed was 2
MHz.
It had 6,000
transistors.
15
Intel 8085 Introduced in 1976.
It was also 8-bit µP.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.
16
16-bit Microprocessors
17
Introduced in 1978.
INTEL 8086 It was first 16bit µP.
Its clock speed is 4.77 MHz, 8
MHz and 10 MHz, depending on
the version.
Its data bus is 16bit and address
bus is 20bit.
It had 29,000 transistors.
Could execute 2.5 million
instructions per second.
It could access 1 MB of memory.
It had 22,000 instructions.
It had Multiply and Divide 18
instructions.
INTEL 8088
Introduced in 1979.
It was also 16bit µP.
It was created as a
cheaper version of
Intel’s 8086.
It was a 16bit processor
with an 8bit external
bus.
19
INTEL 80186 & 80188
Introduced in 1982.
They were 16bit µPs.
Clock speed was 6 MHz.
80188 was a cheaper
version of 80186 with an
8bit external data bus.
20
INTEL 80286
Introduced in 1982.
It was 16bit µP.
Its clock speed was 8
MHz.
Its data bus is 16bit and
address bus is 24bit.
It could address 16 MB
of memory.
It had 1,34,000 21
transistors.
32-BIT
MICROPROCESSORS
22
Introduced in 1986.
INTEL 80386 It was first 32bit µP.
Its data bus is 32bit and
address bus is 32bit.
It could address 4 GB of
memory.
It had 2,75,000
transistors.
Its clock speed varied
from 16 MHz to 33 MHz
depending upon the
various versions. 23
Introduced in 1989.
INTEL 80486
It was also 32bit µP.
It had 1.2 million
transistors.
Its clock speed varied
from 16 MHz to 100
MHz depending upon
the various versions.
8 KB of cache memory
was introduced.
24
Introduced in 1993.
INTEL PENTIUM
It was also 32bit µP.
It was originally named
80586.
Its clock speed was 66
MHz.
Its data bus is 32bit
and address bus is 32
bit.
25
INTEL PENTIUM PRO
Introduced in 1995.
It was also 32bit µP.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
26
INTEL PENTIUM II
Introduced in 1997.
It was also 32bit µP.
Its clock speed was 233
MHz to 500 MHz.
Could execute 333
million instructions per
second.
27
INTEL PENTIUM II XEON
Introduced in 1998.
It was also 32bit µP.
It was designed for
servers.
Its clock speed was 400
MHz to 450 MHz.
28
INTEL PENTIUM III
Introduced in 1999.
It was also 32bit µP.
Its clock speed varied
from 500 MHz to 1.4
GHz.
It had 9.5 million
transistors.
29
INTEL PENTIUM IV
Introduced in 2000.
It was also 32bit µP.
Its clock speed was from
1.3 GHz to 3.8 GHz.
It had 42 million
transistors.
30
Introduced in 2006.
INTEL DUAL CORE
It is 32bit or 64bit µP.
31
32
64-BIT
MICROPROCESSORS
33
Intel Core 2 Intel Core i3
34
INTEL CORE
I5 INTEL CORE I7
35
Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an instruction
• Address: Identification number for memory locations
• Clock: square wave used to synchronize various devices
in µP
• Memory Capacity = 2^n ,
n->no. of address lines
36
BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries data.
2. ADDRESS BUS: group of conducting lines that carries
address.
3.CONTROL BUS: group of conducting lines that carries
control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system 37
TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state
High Impedance: output is not being driven to any defined logic level by
the output circuit.
38
Basic Microprocessors System
Central Processing Unit
Arithmetic-
Control
Logic
Unit
ProcessingUnit
Input Data into Output
Devices Information
Primary Storage Devices
Unit
Keyboard, Monitor
Mouse Printer
etc
1
THE 8086 MICROPROCESSOR
40
UNIT 1 Syllabus
• Introduction to 8086
• Microprocessor architecture
• Addressing modes
• Instruction set
• Assembler directives
• Assembly language programming
• Modular Programming
1.Linking and Relocation
2.Stacks , Procedures , Macros
• Interrupts and interrupt service routines
• Byte & String Manipulation. 41
8086 Microprocessor-introduction
INTEL launched 8086 in 1978
8086 is a 16-bit microprocessor with
• 16-bit Data Bus {D0-D15}
• 20-bit Address Bus {A0-A19} [can access upto
2^20= 1 MB memory locations] .
It has multiplexed address and data bus
AD0-AD15 and A16–A19.
It can support upto 64K I/O ports
42
8086 Microprocessor
It provides 14, 16-bit registers.
8086 requires one phase clock with a 33%
duty cycle to provide optimized internal
timing.
– Range of clock:
• 5 MHz for 8086
• 8Mhz for 8086-2
• 10Mhz for 8086-1
43
8086 Internal Architecture
8086 employs parallel processing
8086 CPU has two parts which operate at the
same time
• Bus Interface Unit 8086 CPU
• Execution Unit
CPU functions Bus Interface
Unit (BIU)
1. Fetch
44
Bus Interface Unit
Sends out addresses for memory
locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input/Output ports
45
Execution Unit
Tells BIU (addresses) where to fetch
instructions or data
Decodes & Executes instructions
46
Architecture Diagram of 8086
47
Memory
∑ Interface
Instruction
Decoder
AH AL
BH BL
ARITHMETIC
CH CL LOGIC UNIT
DH DL CONTROL
SYSTEM
STACK POINTER (SP)
BASE POINTER (BP)
OPERANDS
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
FLAGS
EU 48
Execution Unit
Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers
49
Instruction Decoder
Translates instructions fetched from memory
into a series of actions which EU carries out
Control System
Generates timing and control signals to
perform the internal operations of the
microprocessor
52
Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
57
Instruction Queue
8086 employs parallel processing
When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
58
Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Fetching the next instruction while the
current instruction executes is called
pipelining
59
Memory Segmentation
8086 has a 20-bit address bus
So it can address a maximum of 1MB of
memory
8086 can work with only four 64KB segments
at a time within this 1MB range
These four memory segments are called
• Code segment
• Stack segment
• Data segment
• Extra segment
60
Memory
64KB Memory 1
00000H
Segment 2
3
4
4
5
Only 4 such segments can be 6
addressed at a time 7
8
1MB
9 Address
10 Range
11
12
13
14
15
16
FFFFFH
61
Code Segment
That part of memory from where BIU is
currently fetching instruction code bytes
Stack Segment
A section of memory set aside to store
addresses and data while a subprogram
executes
62
Memory
Code Segment 1
00000H
2
3
4
Segments 6
7
8 1MB
9 Address
10 Range
11
12
13
14
15
16
Stack Segment FFFFFH
63
Segment Registers
hold the upper 16-bits of the starting
address for each of the segments
The four segment registers are
• CS (Code Segment register)
• DS (Data Segment register)
• SS (Stack Segment register)
• ES (Extra Segment register)
64
Memory
1 00000H
CS 1000 0H Code Segment
3
Starting Addresses
8
1MB
9
Address
Range
of Segments
10
11
12
13
14
15
67
Physical Address Calculation Memory
Start of Code Segment 1 00000H
348A0H Data
Segment
IP = 4214H 3
4
Code Byte 38AB4H MOV AL, BL Code
Segment
Extra
Segment
7
8 1MB
9 Address
10
11
Range
CS 348A0 H 12
IP + 4214 H 13
14
Physical Address 38AB4 H 15
Stack
Segment
68
FFFFFH
Stack Segment (SS) Register
Stack Pointer (SP) Register
Upper 16-bits of the starting address of
stack segment is stored in SS register
It is located in BIU
SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
It is located in EU
69
Other Pointer & Index Registers
Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data
word in one of the segments
70
ADDRESSING
MODES OF
8086
71
Various Addressing Modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Index Addressing Mode
6. Based Addressing Mode
7. Based & Indexed Addressing Mode
8. Based & Indexed with displacement Addressing Mode
9. Strings Addressing Mode
72
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
1. IMMEDIATE ADDRESSING MODE
• The instruction will specify the name
of the register which holds the data to
be operated by the instruction.
AL=ABH, AH=10H
73
2.REGISTER ADDRESSING MODE
• In immediate addressing mode, an
8-bit or 16-bit data is specified as
part of the instruction
MOV AX,BL H
74
3. DIRECT ADDRESSING MODE
75
4. REGISTER INDIRECT ADDRESSING MODE
77
6. Based Addressing Mode
• Memory address is the sum of the BX or BP
base register plus a displacement within
instruction
• Ex:
MOV AX,[BP+2] AL [BP+2]; AH [BP+3]
JMP [BX+2] IP [BX+3:BX+2]
78
7.BASED & INDEX ADDRESSING MODES
79
8. BASED & INDEXED WITH DISPLACEMENT ADDRESSING MODE
84
Types of instruction set of 8086
microprocessor
(1). Data Copy/Transfer instructions.
BEFORE AFTER
EXECUTION EXECUTION
A AL A AL
H H
B BL MOV B BL
H CL,M H
C CL 40 C CL 40 40
H H
D D D D
H L H L 87
Stack Pointer
Itis a 16-bit register, contains the address of the
data item currently on top of the stack.
88
(2). Push Source
E.g.:
(1). PUSH AX;
(2). PUSH DS;
(3). PUSH [5000H];
89
INITIAL POSITION
(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE
90
BEFORE EXECUTION
SP 2002H
2000H
BH BL
2001H
CH 10 CL 50
DH DL 2002H
PUSH CX
AFTER EXECUTION
2000H 50
SP 2000H
BH BL
2001H 10
CH 10 CL 50
DH DL 2002H
91
(3) POP Destination
E.g.
(1). POP AX;
(2). POP DS;
(3). POP [5000H];
92
INITIAL POSITION AND READS
LOWER BYTE
(1) STACK
POINTER LOWER BYTE
INCREMENTS SP
LOWER BYTE
HIGHER BYTE
(3) STACK
POINTER
93
BEFORE EXECUTION
2000H30
SP 2000
2001H50
BH H BL
2002H
POP
BX EXECUTION
AFTER
2000H30
SP 2002H 2001H50
BH 5 BL 30 2002H
0 94
(4). XCHG Destination, source;
•E.g.
(1). XCHG BX, AX;
(2). XCHG [5000H],AX;
95
BEFORE EXECUTION AFTER EXECUTION
AH 2 AL 40 AH 70 AL 80
0
BH 7 BL 80 BH 20 BL 40
0
XCHG AX,BX
96
(5)IN AL/AX, 8-bit/16-bit port address
PORT 10 AL
80H
IN AL,80H
AFTER EXECUTION
PORT 10 AL 10
80H
98
OUT 8-bit/16-bit port address, AL/AX
PORT 10 AL 40
50H
OUT 50H,AL
AFTER EXECUTION
PORT 40 AL 40
50H
10
(7) XLAT
10
8.LEA 16-bit register (source),
address (dest.)
LEA Also known as Load Effective
Address (LEA).
It loads effective address formed by
the destination into the source
register.
E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX];
10
(9). LDS 16-bit register (source), address
(dest.);
(10). LES 16-bit register (source), address
(dest.);
LDS Also known as Load Data
Segment (LDS).
LES Also known as Load Extra
Segment (LES).
It loads the contents of DS (Data
Segment) or ES (Extra Segment) &
contents of the destination to the
contents of source register.
E.g.
10
(1). LDS BX,5000H;
(2). LES BX,5000H;
15 0 7 0
BX 20 10 10 5000H
20
5001H
30 5002H
DS/E 40 30
S 40 5003H
10
(11). LAHF:- This instruction loads the AH
register from the contents of lower byte of the
flag register.
This command is used to observe the status
of the all conditional flags of flag register.
E.g. LAHF;
Addition,
Subtraction,
Increment,
Decrement.
10
(2). Arithmetic
Instructions
(1). ADD destination, source;
AH 10 AL 10 AH 30 AL 30
ADD
BH 20 BL 20 AX,BX BH 20 BL 20
10
ADC destination, source
This instruction adds the contents of source
operand with the contents of destination
operand with carry flag bit.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in destination operand.
AX is the default destination register.
AH 10 AL 11 INC AX AH 10 AL 12
AH 10 AL 11 DEC AH 10 AL 10
AX
AH 20 AL 00 SUB AH 10 AL 00
AX,1000H
2000
-1000
=1000
AH 20 AL 00 AH 10 AL 00
BH 10 BL 00
SUB BH 10 BL 00
AX,BX
11
(6). SBB destination,
source;
Also known as Subtract with Borrow.
This instruction subtracts the contents of
source operand & borrow from contents of
destination operand.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in the destination place.
B 1 SBB AX,1000H
AH 20 AL 20 AH 10 AL 19
2020
- 1000
1020-
BEFORE EXECUTION 1=1019 AFTER EXECUTION
B 1
AH 20 AL 20 AH 10 AL 19
SBB AX,BX
BH 10 BL 10 BH 10 BL 10
2050
11
(7). CMP destination,
source
Also known as Compare.
This instruction compares the contents of
source operand with the contents of
destination operands.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
Then resulting carry & zero flag will be set or
reset.
12
AAA (ASCII Adjust after Addition):
The data entered from the terminal is in ASCII format.
12
IMUL operand
Signed Multiplication.
Operand contents are negatively signed.
Operand may be general purpose register, memory
location or index register.
If operand is of 8-bit then multiply it with contents of
AL.
If operand is of 16-bit then multiply it with contents of
AX.
Result is stored in accumulator (AX).
12
DIV operand
Unsigned Division.
Operand may be register or memory.
Operand contents are positively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
12
BEFORE EXECUTION
AH 00 AL 05
BH 00 BL 03
CH CL
BX
AFTER EXECUTION 0005*0003 = 0000 000F
AH 00 AL 0F
BH BL
CH CL
DH 00 DL 00
12
BEFORE EXECUTION
AH 00 AL 0F
BH 00 BL 02
CH CL AX=Quotient {0007}
DX=Reminder {0001}
DIV BX 000F =7 1
AH 00 AL 07
BH BL
CH CL
DH 00 DL 01
12
13
13
13
LOGICAL (or) Bit
Manipulation Instructions
These instructions are used at the bit level.
133
Bit Manipulation Instructions(LOGICAL
Instructions)
• AND
– Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
– Examples: AND BL, 0FH
• OR
– Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)
134
XOR
– Used in Inverting bits
135
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH 11 AL 11
AND AX,BXH
BH 11 BL 11 BH 11 BL 11
13
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH FF AL FF
OR AX,BXH
BH 11 BL 11 BH 11 BL 11
13
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH EE AL EE
XOR
BH 11 BL 11 AX,BXH BH 11 BL 11
13
AFTER EXECUTION
BEFORE EXECUTION
AH FF AL FF AH 00 AL 00
NOT AXH
13
SHL Instruction
The SHL (shift left) instruction performs a
logical left shift on the destination operand,
filling the lowest bit with 0.
0
CF
mov dl,5d
shl dl,1
140
SHR Instruction
The SHR (shift right) instruction performs a
logical right shift on the destination
operand. The highest bit position is filled
with a zero.
0
CF
MOV DL,80d
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
141
SAR Instruction
SAR (shift arithmetic right) performs
a right arithmetic shift on the
destination operand.
CF
For example, 80 / 23 = 10
Before: 0 0 0 0 0 1 0 1 = 5
mov dl,5
After: 0 0 0 0 1 0 1 0 = 10
shl dl,1
143
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the
Carry flag and into the lowest bit
No bits are lost
CF
MOV Al,11110000b
ROL Al,1 ; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
144
ROR Instruction
ROR (rotate right) shifts each bit to the
right
The lowest bit is copied into both the
Carry flag and into the highest bit
No bits are lost
CF
MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h
145
RCL Instruction
RCL (rotate carry left) shifts each bit to the
left
Copies the Carry flag to the least significant
bit
Copies
CF the most significant bit to the Carry
flag
CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
146
RCR Instruction
RCR (rotate carry right) shifts each bit to
the right
Copies the Carry flag to the most
significant bit
Copies the least significant bit to theCF
Carry flag
STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0
147
SHL Instruction
The SHL (shift left) instruction performs a
logical left shift on the destination
operand, filling the lowest bit with 0.
0
CF
BEFORE
0 0 0 0 0 1 0 1 =05H
EXECUTION
CF
0 0 0 0 1 0 1 0 =0AH
AFTER 0
EXECUTION
14
SHR Instruction
0
CF
BEFORE
0 0 0 0 0 1 0 1 =05H
EXECUTION
CF
AFTER 0 0 0 0 0 0 1 0 1
EXECUTION
=02H
14
ROL Instruction
CF
BEFORE
EXECUTION 0 0 0 0 0 1 0 1 =05H
CF
AFTER 0 0 0 0 0 1 0 1 0 =0AH
EXECUTION
15
ROR Instruction
CF
BEFORE 0 0 0 0 0 1 0 1 =05H
EXECUTION
CF
AFTER 1 0 0 0 0 0 1 0 1 =82H
EXECUTION
15
Branching Instructions
(or)
Program Execution
Transfer Instructions
These instructions cause change in the
sequence of the execution of instruction.
This change can be through a condition or
sometimes unconditional.
The conditions are represented by flags.
152
CALL Des:
Main
program
Subroutine A
First
Instruction
Call
subroutine
Next A
instruction
Return
Call
subroutine
Next A
instruction
154
JMP Des:
155
Conditional Jump Table
Mnemonic Meaning
JA Jump if Above
JAE Jump if Above or Equal
JB Jump if Below
JBE Jump if Below or Equal
JC Jump if Carry
JE Jump if Equal
JNC Jump if Not Carry
JNE Jump if Not Equal
JNZ Jump if Not Zero
JPE Jump if Parity Even
JPO Jump if Parity Odd
JZ Jump if Zero
156
Loop Des:
157
String
Instructions
String in assembly language is just a
sequentially stored bytes or words.
There are very strong set of string instructions
in 8086.
By using these string instructions, the size of
the program is considerably reduced.
158
CMPS Des, Src:
SCAS String:
159
MOVS / MOVSB / MOVSW:
160
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
161
2. Find & Replace
162
REP (Repeat):
163
Processor Control
Instructions
These instructions control the processor itself.
164
STC
It sets the carry flag to 1.
CLC
It clears the carry flag to 0.
CMC
It complements the carry flag.
165
STD:
It sets the direction flag to 1.
CLD:
It clears the direction flag to 0.
166
HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop
fetching and executing instructions.
NOP instruction
this instruction simply takes up three clock cycles
and does no processing.
LOCK instruction
this is a prefix to an instruction. This prefix
makes sure that during execution of the instruction,
control of system bus is not taken by other
microprocessor.
WAIT instruction
this instruction takes 8086 to an idle
167 condition. The CPU will not do any
INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS
168
2. ARITHMETIC INSTRUCTIONS
Mnemonic Meaning Format Operation
ADC Add with carry ADC D,S (S)+(D)+(CF) (D) carry (CF)
170
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
Shift & Rotate Instructions
Mnemonic Meaning Format
SAL/SHL Shift arithmetic Left/ SAL/SHL D, Count
Shift Logical left
171
4. Branching or PROGRAM EXECUTION
TRANSFER INSTRUCTIONS
• CALL - call a subroutine
• RET - returns the control from procedure to calling
program
• JMP Des – Unconditional Jump
• Jxx Des – conditional Jump (ex: JC 8000)
• Loop Des
172
5. STRING INSTRUCTIONS
• CMPS Des, Src - compares the string bytes
• SCAS String - scans a string
• MOVS / MOVSB / MOVSW - moving of byte or
word
• REP (Repeat) - repetition of the instruction
173
6. PROCESSOR CONTROL INSTRUCTIONS
• STC – set the carry flag (CF=1)
• CLC – clear the carry flag (CF=0)
• STD – set the direction flag (DF=1)
• CLD – clear the direction flag (DF=0)
• HLT – stop fetching & execution
• NOP – no operation(no processing)
• LOCK - control of system bus is not taken by other µP
• WAIT - CPU will not do any processing
• ESC - µP does NOP or access a data from memory for coprocessor
174
Assembler
Directives
175
Directives Expansion
176
• ASSUME Directive - The ASSUME directive is
used to tell the assembler that the name of
the logical segment should be used for a
specified segment.
• DB(define byte) - DB directive is used to
declare a byte type variable or to store a byte
in memory location.
• DW(define word) - The DW directive is used
to define a variable of type word or to reserve
storage location of type word in memory.
180
Directives examples
• ASSUME CS:CODE cs=> code segment
• ORG 3000
• NAME DB ‘THOMAS’
• POINTER DD 12341234H
• FACTOR EQU 03H
181
Assembly Language
Programming(ALP)
8086
182
Program 1: Increment an 8-bit number
184
Program 5: 1’s complement of an 8-bit
number.
• MOV AL, 05H Move 8-bit data to AL.
• NOT AL Complement AL.
After Execution AL = FAH
185
Program 7: 2’s complement of an 8-bit
number.
• MOV AL, 05H Move 8-bit data to AL.
• NOT AL Complement AL.
• INC AL Increment AL
After Execution AX = FAH + 1 = FB
186
Program 9: Add two 8-bit numbers
MOV AL, 05H Move 1 8-bit number to AL.
st
187
Program 11: subtract two 8-bit numbers
MOV AL, 05H Move 1 8-bit number to AL.
st
189
Program 15: Multiply two 16-bit unsigned
numbers.
MOV AX, 0004H Move 1st 16-bit number to AL.
MOV BX, 0002H Move 2nd 16-bit number to BL.
MUL BX Multiply BX with AX and the result will
be in DX:AX {4*2=0008=> 08=> AX , 00=> DX}
191
Detailed coding
16 BIT SUBTRACTION
192
16 BIT MULTIPLICATION
193
16 BIT DIVISION
194
SUM of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN SUM
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
195
Average of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN AVERAGE
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
DIV CX AX=AX/5(AVERAGE OF 5 NUMBERS)
MOV [1200],AX
HLT
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,
196Erode
FACTORIAL of N
MOV CX,0005 5 Factorial=5*4*3*2*1=120
MOV DX,0000
MOV AX,0001
L1: MUL CX
DEC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
197
ASCENDING ORDER
198
199
DECENDING ORDER
201
LARGEST NUMBER
202
SMALLEST NUMBER
203
Modular
Programming
204
• Generally , industry-programming projects consist of
thousands of lines of instructions or operation code.
• The size of the modules are reduced to a humanly
comprehensible and manageable level.
• Program is composed from several smaller
modules. Modules could be developed by
separate teams concurrently.OBJ modules (Object
modules).
• The .OBJ modules so produced are combined using a
LINK program.
• Modular programming techniques simplify the
software development process
205
CHARACTERISTICS of module:
1. Each module is independent of other modules.
2. Each module has one input and one output.
3. A module is small in size.
4. Programming a single function per module is a goal
Advantages of Modular Programming:
• It is easy to write, test and debug a module.
• Code can be reused.
• The programmer can divide tasks.
• Re-usable Modules can be re-used within a program
DRAWBACKS:
Modular programming requires extra time and memory
206
MODULAR PROGRAMMING:
1.LINKING & RELOCATION
2.STACKS
3.Procedures
4.Interrupts & Interrupt Routines
5.Macros
207
LINKING &
RELOCATION
208
LINKER
• A linker is a program used to join together several object
files into one large object file.
• The linker produces a link file which contains the binary
codes for all the combined modules.
210
Creation and execution of a program
211
Loader
->Loader is a utility program which takes object code as
input prepares it for execution and loads the executable
code into the memory .
->Loader is actually responsible for initializing the process
of execution.
Functions of loaders:
1.It allocates the space for program in the memory(Allocation)
2.It resolves the code between the object modules(Linking)
3. some address dependent locations in the program, address constants
must be adjusted according to allocated space(Relocation)
4. It also places all the machine instructions and data of corresponding
programs and subroutines into the memory .(Loading)
212
Relocating loader (BSS Loader)
• When a single subroutine is changed then all the
subroutine needs to be reassembled.
• The binary symbolic subroutine (BSS) loader used
in IBM 7094 machine is relocating loader.
• In BSS loader there are many procedure
segments
• The assembler reads one sourced program and
assembles each procedure segment
independently
213
• The output of the relocating loader is the object program
• The assembler takes the source program as input; this source
program may call some external routines.
SEGMENT COMBINATION:
ASM-86 assembler regulating the way segments with the same
name are concatenated & sometimes they are overlaid.
Form of segment directive:
Segment name SEGEMENT Combine-type
Possible combine-type are:
• PUBLIC
• COMMON
• STACK
• AT
• MEMORY
214
Procedures
CALL & RET instruction
215
• Procedure is a part of code that can be called from
your program in order to make some specific task.
Procedures make program more structural and
easier to understand.
• syntax for procedure declaration:
name PROC
…………. ; here goes the code
…………. ; of the procedure ...
RET
name ENDP
here PROC is the procedure name.(used in top & bottom)
RET - used to return from OS. CALL-call a procedure
PROC & ENDP – complier directives
CALL & RET - instructions 216
EXAMPLE 1 (call a procedure)
ORG 100h
CALL m1
MOV AX, 2
RET ; return to operating system.
m1 PROC
MOV BX, 5
RET ; return to caller.
m1 ENDP
END
• The above example calls procedure m1, does MOV BX, 5 &
returns to the next instruction after CALL: MOV AX, 2.
m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP
END value of AL register is update every time the
procedure is called.
final result in AX register is 16 (or 10h)
STACK
PUSH & POP instruction
219
• Stack is an area of memory for keeping
temporary data.
• STACK is used by CALL & RET instructions.
PUSH -stores 16 bit value in the stack.
POP -gets 16 bit value from the stack.
• PUSH and POP instruction are especially useful
because we don't have too much registers to operate
1. Store original value of the register in stack (using
PUSH).
2. Use the register for any purpose.
3. Restore the original value of the register from stack
(using POP).
220
Example-1 (store value in STACK using PUSH
& POP)
ORG 100h
MOV AX, 1234h
PUSH AX ; store value of AX in stack.
MOV AX, 5678h ; modify the AX value.
POP AX ; restore the original value of AX.
RET
END
221
Example 2: use of the stack is for
exchanging the values
ORG 100h
MOV AX, 1212h ; store 1212h in AX.
MOV BX, 3434h ; store 3434h in BX
PUSH AX ; store value of AX in stack.
PUSH BX ; store value of BX in stack.
POP AX ; set AX to original value of BX.
POP BX ; set BX to original value of AX.
RET
END
push 1212h and then 3434h, on pop we will
first get 3434h and only after it 1212h 222
MACROS
How to pass parameters using macros-6/8 Mark
223
• Macros are just like procedures, but not really.
• Macros exist only until your code is compiled
• After compilation all macros are replaced with
real instructions
• several macros to make coding easier(Reduce
large & complex programs)
Example (Macro definition)
name MACRO [parameters,...]
<instructions>
ENDM
224
Example1 : Macro Definitions
SAVE MACRO definition of MACRO name SAVE
PUSH AX
PUSH BX
PUSH CX
ENDM
225
226
MACROS with Parameters
Example:
COPY MACRO x, y ; macro named COPY with
2 parameters{x, y}
PUSH AX
MOV AX, x
MOV y, AX
POP AX
ENDM
227
INTERRUPTS
&
INTERRUPT SERVICE
ROUTINE(ISR)
228
INTERRUPT & ISR ?
• ‘Interrupts’ is to break the sequence of
operation.
• While the CPU is executing a program, on
‘interrupt’ breaks the normal sequence of
execution of instructions, diverts its execution
to some other program called Interrupt
Service Routine (ISR)
229
230
231
232
• Maskable Interrupt: An Interrupt that can be
disabled or ignored by the instructions of CPU
are called as Maskable Interrupt.
• Non- Maskable Interrupt: An interrupt that
cannot be disabled or ignored by the instructions
of CPU are called as Non- Maskable Interrupt.
• Software interrupts are machine instructions
that amount to a call to the designated interrupt
subroutine, usually identified by interrupt
number. Ex: INT0 - INT255
233
234
235
236
237
238
INTERRUPT VECTOR TABLE
NMI(INT2)
INTR
241
Byte &
String
Manipulation
242
Move, compare, store, load, scan
243
Byte Manipulation
Example 3:
Example 1:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
MOV BX,[1002]
AND AX,BX XOR AX,BX
MOV [2000],AX MOV [2000],AX
HLT HLT
Example 2: Example 4:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
OR AX,BX
NOT AX
MOV [2000],AX MOV [2000],AX
HLT HLT
244
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
STRING MANIPULATION
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
245
2. Find & Replace
246
UNIT-2
8086 SYSTEM BUS
STRUCTURE
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech , Erode
247
UNIT 2 Syllabus
248
8086 signals or
Pin Diagram
249
INTEL 8086-Pin Diagram/Signal Description
250
INTEL 8086 - Pin Details
Power Supply
5V 10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
251
INTEL 8086 - Pin Details
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.
252
INTEL 8086 - Pin Details
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
253
INTEL 8086 - Pin Details
Direct
Memory
Access
Hold
Hold
acknowledge
254
INTEL 8086 - Pin Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3
255
INTEL 8086 - Pin Details
1,1: No selection
256
INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Maximum Mode
Pins
257
Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.
259
Maximum Mode - Pin Details
Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the
Request/Grant
LOCK: prefix on any
instruction
Lock Output
260
Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
261
Minmode operation
signals (MN/MX=1) Time-
0V=“0”, GND 1 40 Vcc multiplexed
AD14 AD15 5V±10%
reference Address Bus
for all AD13 A16/S3 /Status signals
voltages AD12 A17/S4 Maxmode operation (outputs)
AD11 A18/S5 signals (MN/MX=0)
AD10 A19/S6
AD9 ___ Control Operation Mode,
AD8 BHE/S7 (HIGH) Bus (input):
Time-multiplexed AD7 INTEL ___ (in,out) 1 = minmode
Address / Data Bus AD6 8086 MN/MX
(8088 generates all
(bidirectional) AD5 ___
the needed control
AD4 RD
signals for a small
AD3 ___ ____ Status system),
Hardware AD2 HOLD (RQ/GT0)signals
interrupt AD1 ___ ____ (outputs)
0 = maxmode
requests (inputs) AD0 HLDA (RQ/GT1)
(8288 Bus
NMI ___ ______
Controller expands
2...5MHz, INTR WR (LOCK) Interrupt the status signals
1/3 duty cycle CLK __ __ acknowledge
to generate more
(input) GND 20 21 IO/M (S2) (output) control signals)
262
__ __
Timing
Diagram
Basics
only for understanding
System Timing Diagrams
T-State:
— One clock period is referred to as a T-State
T-State
T1 T2 T3 T4
265
Signal Transition
occurs when the clock
signal is HIGH
Signal Transition
occurs when the clock
signal is LOW
Signal Transition
occurs from HIGH to
LOW on RISING EDGE
AD0-AD15
SYSTEM BUS
TIMING
272
Memory Read Timing Diagrams
273
Memory Write Timing Diagrams
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.
274
Bus Timing
During T 1 :
• The address is placed on the Address/Data bus.
• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
• 8086 issues the RD or WR signal, DEN , and, for a write, the data.
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
• This cycle is provided to allow memory to access data.
• READY is sampled at the end of T 2 .
• If low, T 3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
• All bus signals are deactivated, in preparation for next bus cycle.
• Data is sampled for reads, writes occur for writes.
275
Setup & Hold Time
Setup time – The time before the rising edge of the clock, while the data
must be valid and constant
Hold time – The time after the rising edge of the clock during which the data
must remain valid and constant
276
WAIT State
279
1.Minimum
Mode
configuration
Minimum Mode 8086 System
• 8086 is operated in minimum mode by
MN/MX pin to logic 1 ( Vcc ).
• In this mode, all the control signals are given
out by the microprocessor chip itself.
283
284
Memory READ in Minimum Mode
Memory WRITE in Minimum Mode
2.Maximum
Mode
configuration
NOTE: Explain Maximum mode signals also {refer pin diagram}
MAXIMUM MODE SIGNALS
288
8288 – BUS CONTROLLER
289
MAXIMUM MODE
290
291
292
MULTIPROCESSOR
CONFIGURATIONS
293
Coprocessor 8087
Multiprocessor
configuration
294
Multiprocessor configuration
• Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.
296
Co-processor – Intel 8087
8086 and 8087 reads
instruction bytes and puts
8087 instructions them in the respective queues
are inserted in
the 8086 NOP
program
8087 instructions have 11011
as the MSB of their first code
byte
297
Coprocessor / Closely Coupled Configuration
298
TEST pin of 8086
• Used in conjunction with the WAIT instruction in
multiprocessing environments.
299
1.Coprocessor Execution Example
Coprocessor cannot take control of the bus, it does everything through the CPU
300
2.Closely Coupled Execution Example
• Closely Coupled
processor may take
control of the bus
independently.
301
3.Loosely Coupled Configuration
• has shared system bus, system memory, and system
I/O.
1. Daisy Chaining:
- Need a bus controller to monitor bus busy and bus request
signals
- Sends a bus grant to a Master >> each Master either keeps the
service or passes it on
- Controller synchronizes the clocks
- Master releases the Bus Busy signal when finished
Daisy Chaining:
Independent
Advantages of Multiprocessor Configuration
1. High system throughput can be achieved by having more than
one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on
a separate PC board. One can be added or removed without affecting the
others in the system.
80286 16 24 16M
80386 DX 32 32 4G
80486 32 32 4G
Pentium 4 & 64 40 1T
core 2
312
80286
313
80386
314
UNIT-3
315
I/O
INTERFACING
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech ,
Erode
UNIT 3 Syllabus
• Memory Interfacing & I/O interfacing
• Parallel communication interface {8255 PPI}
• Serial communication interface {8251 USART}
• D/A and A/D Interface {ADC 0800/0809,DAC 0800}
• Timer {or counter} – {8253/8254 Timer}
• Keyboard /display controller {8279}
• Interrupt controller {8259}
• DMA controller {8237/8257}
• Programming and applications Case studies
1.Traffic Light control 2.LED display
3.LCD display 4.Keyboard display interface
5.Alarm Controller
316
317
Data Transfers
Synchronous ----- Usually occur
when peripherals are located within
the same computer as the CPU. Close
proximity allows all state bits change
at same time on a common clock.
Asynchronous ----- Do not require
that the source and destination use
the same system clock.
318
Parallel communication
interface
INTEL 8255
8255 PPI
• The 8255 chip is also called as Programmable
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s
8-bit, 16-bit and higher capability
microprocessors
• The 8255 is a 40 pin integrated circuit (IC),
designed to perform a variety of interface
functions in a computer environment.
• It is flexible and economical.
324
Signals of 8085
8255 PIO/PPI
326
Control Logic
CS signal is the master Chip Select
A0 and A1 specify one of the two I/O
Ports
CS A1 A0 Selecte
d
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is
not
Block Diagram of 8255A 330
331
CS , RD , WR , RESET , A1 , A0
334
1. BSR Mode
339
Bit/pin of port C
B3 B2 B1
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
interrupt capability
341
342
Solution:
1 0 1 0 1 1 1 0 = AEH
345
Solution:
1 0 0 0 0 0 0 0 = 80H
Solution:
1 0 0 1 1 0 1 1 = 9BH
- A serial-in, parallel-out
shift register.
-
347
TRANSMITTER 348
Receiver
349
Serial communication
interface
INTEL 8251 USART
350
Five Sections
– Read/Write Control Logic
• Interfaces the chip with MPU
– Transmitter
• Converts parallel word received from MPU into serial bits
– Receiver
• Receives serial bits from peripheral
telephone line
354
Input Signals
CS – Chip Select
When this signal goes low, 8251 is selected by
MPU for communication
C/D – Control/Data
When this signal is high, the control register
or status register is addressed
When it is low, the data buffer is addressed
Control and Status register is differentiated by
WR and RD signals, respectively
355
• WR – Write
– writes in the control register or sends outputs
to the data buffer.
– This connected to IOW or MEMW
• RD – Read
– Either reads a status from status register or
accepts data from the data buffer
– This is connected to either IOR or MEMR
• RESET - Reset
• CLK - Clock
– Connected to system clock
– Necessary for communication with
microprocessor.
356
CS C/ RD WR Function
D
0 1 1 0 MPU writes instruction in the
control register
0 1 0 1 MPU reads status from the status
register
0 0 1 0 MPU outputs the data to the Data
Buffer
0 0 0 1 MPU accepts data from the Data
Buffer
1 X X X USART is not Selected
357
• Control Register
– 16-bit register
– This register can be accessed an output port
when the C/D pin is high
• Status Register
– Checks ready status of a peripheral
• Data Buffer
358
Transmitter Section
register is empty
360
Receiver Section
Control words
364
365
366
367
368
Interfacing of 8255(PPI) with 8085 processor
369
11-
370
Programming 8251
8251 mode register
7 6 5 4 3 2 1 0 Mode register
ADC 0808/0809
The analog to digital converter chips
0808 and 0809 are 8-bit
CMOS,successive approximation
converters.
Successive approximation
technique is one of the fast
techniques for analog to digital
conversion. The conversion delay is
100 µs at a clock frequency of 640
kHz.
375
TIMER/COUNTER
INTEL 8253/8254
386
Pin diagram
RD: read signal 387
11-390
8254 Modes
Gate is low the
count will be Mode 0: An events counter enabled with G.
paused
N 1 2 2 2 3 4 5
CLK
Gate is high
OUT
Will continue
counting
GATE
count of 5 load
Mode 1: One-shot mode. s Counter will be reloaded
After gate high.
1 2 3 4 5
CLK Gate is
High output
GATE will be high
391
OUT trigger with count of 5
Mode 2: Counter generates a series of pulses 1 clock
pulse wide
1 2 3 4 5 1 2 3 4 5 1
CLK
1 2 3 4 1 2 3 4
CLK
OUT
If count is even, 50% duty cycle
count of 6 loaded otherwise OUT is high 1 cycle 392
longer
Mode 4: Software triggered one-shot.
1 2 3 4 5 6 7 8
CLK
OUT
Trigger with count of 8 In the last counting
Will be stop
(not repeated)
GATE
Keyboard/Display
Controller
INTEL 8279
395
Introduction
The INTEL 8279 is specially
developed for interfacing
keyboard and display devices to
8085/8086 microprocessor based
system
396
Features of 8279
Simultaneous keyboard and
display operations
Scanned keyboard mode
Scanned sensor mode
8-character keyboard FIFO
1 6-character display
397
Pin Diagram
398
4 sections
Keyboard section
Display section
Scan section
Keyboard section
The keyboard section consists of
8 return lines RL0 - RL7 that can
be used to form the columns of a
keyboard matrix.
It has two additional input : shift
and control/strobe. The keys are
automatically debounced.
The two operating modes of
keyboard section are 2-key
lockout and N-key rollover.
In the 2-key lockout mode, if two 402
Display section
Scan section
The scan section has a scan counter
and four scan lines, SL0 to SL3.
In decoded scan mode, the output of
scan lines will be similar to a 2-to-4
decoder.
In encoded scan mode, the output of
scan lines will be binary count, and so
an external decoder should be used
to convert the binary count to
decoded output.
The scan lines are common for
406
SENSOR MATRIX
SENSOR MATRIX
410
B) Programmable clock :
0 0 1 P P P P P
411
c)Read FIFO / Sensor RAM : The format of this
command is given below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
E- Error mode
X- don’t care
INTERRUPT
CONTROLLER
INTEL 8259
8259 Programmable Interrupt Controller (PIC)
1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
8. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
8259A PIC- PIN DIGRAM
8259
ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave in a
system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master, and is
connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system. In a
system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
When the 8259A is in buffered mode, this pin is an
output that controls the data bus transceivers in a
large microprocessor-based system.
When the 8259A is not in buffered mode, this pin
programs the device as a master (1) or a slave (0).
CAS2-CAS0, the cascade lines are used as outputs from
the master to the slaves for cascading multiple 8259As
in a system.
8259A PIC- BLOCK DIAGRAM
Programming the 8259A: -
The 82C59A accepts two types of command words generated by the
CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 82C59A in the
system must be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
2. Operational Command Words (OCWs):
These are the command words which command the 82C59A
to operate in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
ICW1:
Selects the vector number used with the interrupt request inputs.
For example, if we decide to program the 8259A so that it functions at vector
locations 08H-0FH, we place a 08H into this command word.
Likewise, if we decide to program the 8259A for vectors 70H-77H, we place a
70H in this ICW.
ICW3:
Is used only when ICW1 indicates that the system is operated in cascade mode.
This ICW indicates where the slave is connected to the master.
For example, if we connected a slave to IR2, then to program ICW3 for this
connection, in both master and slave, we place a 04H in ICW3.
Suppose we have two slaves connected to a master using IR0 and IR1. The
master is programmed with an ICW3 of 03H; one slave is programmed with an
ICW3 of 01H and the other with an ICW3 of 02H.
ICW4:
Is programmed only when the AEOI mod is not selected for the 8259A.
In this case, this OCW selects how the 8259A responds to an interrupt.
The modes are listed as follows in next slide:
OCW3:
Selects the register to be read, the operation of the special mask register, and
the poll command.
If polling is selected, the P-bit must be set and then output to the 8259A. The
next read operation would read the poll word. The rightmost three bits of the
poll word indicate the active interrupt request with the highest priority.
The leftmost bit indicates whether there is an interrupt, and must be checked
to determine whether the rightmost three bits contain valid information.
8237DMA CONTROLLER
449
Introduction:
Direct Memory Access (DMA) is a method of allowing
data to be moved from one location to another in a
computer without intervention from the central
processor (CPU).
It is also a fast way of transferring data within (and
sometimes between) computer.
The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily
disabled.
The DMA controller temporarily borrows the address
bus, data bus and control bus from the microprocessor
and transfers the data directly from the external devices
to a series of memory locations (and vice versa).
450
The 8237 DMA controller
• Supplies memory and I/O with control signals and addresses during DMA
transfer
• 4-channels (expandable)
– 0: DRAM refresh
– 1: Free
– 2: Floppy disk controller
– 3: Free
• 1.6MByte/sec transfer rate
• 64 KByte section of memory address capability with single programming
• “fly-by” controller (data does not pass through the DMA-only memory to I/O
transfer capability)
• Initialization involves writing into each channel:
• i) The address of the first byte of the block of data that must be transferred (called
the base address).
• ii) The number of bytes to be transferred (called the word count).
451
8237 pins
• CLK: System clock
• CS΄: Chip select (decoder output)
• RESET: Clears registers, sets mask register
• READY: 0 for inserting wait states
• HLDA: Signals that the μp has relinquished buses
• DREQ3 – DREQ0: DMA request input for each channel
• DB7-DB0: Data bus pins
• IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
• IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or
as output to signal the end of the DMA transfer
• A3-A0: Address pins for selecting internal registers
• A7-A4: Outputs that provide part of the DMA transfer address
• HRQ: DMA request output
• DACK3-DACK0: DMA acknowledge for each channel.
• AEN: Address enable signal
• ADSTB: Address strobe
• MEMR΄: Memory read output used in DMA read cycle
• MEMW΄: Memory write output used in DMA write cycle
452
8237 block diagram
453
Block Diagram Description
454
DATA BUS BUFFER:
It contain tristate ,8 bit bi-directional buffer.
Slave mode ,it transfer data between
microprocessor and internal data bus.
Master mode ,the outputs A8-A15 bits of
memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC:
It control all internal Read/Write operation.
Slave mode ,it accepts address bits and control
signal from microprocessor.
Master mode ,it generate address bits and control
signal.
455
Control logic block
It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
Master mode ,It control the sequence of DMA
operation during all DMA cycles.
It generates address and control signals.
It increments 16 bit address and decrement 14 bit
counter registers.
It activate a HRQ signal on DMA channel Request.
Slave ,mode it is disabled.
456
DMA controller details
457
Programming
and applications
Case studies
1.Traffic Light control
2.LED display
3.LCD display
4.Keyboard display interface
458 5.Alarm Controller
1. TRAFFIC
LIGHT
CONTROL
459
Traffic lights, which may also be known as
stoplights, traffic lamps, traffic signals,
signal lights, robots or semaphore, are
signaling devices positioned at road
intersections, pedestrian crossings and
other locations to control competing flows
of traffic.
INTERFACING TRAFFIC LIGHT WITH
8086
The Traffic light controller section
consists of 12 Nos. point led’s arranged by
4Lanes in Traffic light interface card. Each
lane has Go(Green), Listen(Yellow) and
Stop(Red) LED is being placed.
460
LAN Direction 8086 LINES MODULES
PA.0 GO
SOUTH PA.1 LISTEN
PA.2 STOP
PA.3 GO
EAST PA.4 LISTEN
PA.5 STOP
PA.6 GO
NORTH PA.7 LISTEN
PB.0 STOP
PB.1 GO
WEST PB.2 LISTEN
PB.3 STOP
13-16 No Connection
17,189 Supply from
PWR
18,20 microcontroller
461
CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH
8086
462
8086 ALP:
1100: START: MOV BX, 1200H
MOV CX, 0008H
MOV AL,[BX]
MOV DX, CONTROL PORT
OUT DX, AL
INC BX
NEXT: MOV AL,[BX]
MOV DX, PORT A
OUT DX,AL
CALL DELAY
INC BX
LOOP NEXT
JMP START
DELAY: PUSH CX
MOV CX,0005H
REPEAT: MOV DX,0FFFFH
LOOP2: DEC DX
JNZ LOOP2
LOOP REPEAT
POP CX
463 RET
Lookup Table
1200 80H
1201 21H,09H,10H,00H (SOUTH WAY)
1205 0CH,09H,80H,00H (EAST WAY)
1209 64H,08H,00H,04H (NOURTH WAY)
120D 24H,03H,02H,00H (WEST WAY)
1211 END
464
2. LED
DISPLAY
465
Light Emitting Diodes (LED) is the most
commonly used components, usually for
displaying pins digital states. Typical uses of
LEDs include alarm devices, timers and
confirmation of user input such as a mouse
click or keystroke.
INTERFACING LED
Anode is connected through a resistor to
GND & the Cathode is connected to the
Microprocessor pin. So when the Port Pin is
HIGH the LED is OFF & when the Port Pin is
LOW the LED is turned ON.
466
PIN ASSIGNMENT WITH
8086
467
INTERFACE LED WITH
8255
468
8086 ALP LED interface
1100: START: MOV AL, 80
MOV DX, FF36
OUT DX, AL
BEGIN: MOV AL, 00
MOV DX, FF30
OUT DX, AL
CALL DELAY
MOV AL, FF
OUT DX, AL
CALL DELAY
JMP BEGIN
DELAY: MOV CX, FFFF
PO: DEC CX
JNE PO
469 RET
3. LCD
DISPLAY
470
471
HARDWARE CONFIGURATION OF
LCD WITH 8051/8086/8085
472
LCD INTERFACING WITH 8086
TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24
473
474
LCD INTERFACING WITH 8051
Used in UNIT 5
also
TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port 4003
PORT A 4000
PORT B 4001
PORT C 4002
475
476
4. Keyboard display
interface
477
HARDWARE DESCRIPTION OF 8279 INTERFACE CARD
Keyboard and display is configured in the encoded mode.
In the encoded mode, a binary count sequence is put on
the scan lines SL0-SL3. These lines must be externally
decoded to provide the scan lines for keyboard and
display. A 3 to 8 decoder 74LS138 is provided for this
purpose. The S0-S1 output lines of this decoder are
connected to the two rows of the keyboard. And QA0 to
QA7 is connected to 7 Segment Display
478
479
5. ALARM
CONTROLLER
Relevant
Material
Not exact
484
GPIO- I J1 Connecter
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24
GPIO- II J1 Connecter
PORTS ADDRESS
Control port FF36
PORT A FF30
PORT B FF32
PORT C FF34
486
Basics
Microprocessor &
Microcontroller
487
What is Microcontroller?
Micro Controller
Microprocessors
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example: Intel's x86, Motorola’s
680x0
489
Microcontroller
A smaller computer
On-chip RAM, ROM, I/O ports...
Example: Motorola’s 6811, Intel’s 8051,
Zilog’s Z8 and PIC
490
491
Microprocessor Microcontroller
CPU is stand-alone,
CPU, RAM, ROM, I/O and
timer are all on a single
RAM, ROM, I/O, timer chip
are separate
Fix amount of on-chip
Designer can decide ROM, RAM, I/O ports
on the amount of
ROM, RAM and I/O
For applications in which
cost, power and space are
ports. critical
Expansive Not Expansive
General-purpose Single-purpose
492
Microcontrollers Applications
Home
Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.
Office
Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, color printer, paging etc.
Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
493
494
UNIT-4
8051
MICROCONTROLLER
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech ,
Erode
UNIT 4 Syllabus
• Architecture of 8051
• Special Function Registers(SFRs)
• I/O Pins Ports and Circuits {Pin Diagram}
• Instruction set
• Addressing modes
• Assembly language programming
495
496
8051 Family
The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
Add external ROM to it
You lose two ports, and leave only 2 ports
for I/O operations
497
Introduction to
8051
MICROCONTROLLER
498
8051 Microcontroller
Intel introduced 8051, developed in the year
1981.
The 8051 is an 8-bit controller.
D0-D7 DATA LINES
A0-A15 ADDRESS LINES
General Block Diagram of 8051 499
External Interrupts
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
8051 Features 500
8 bit CPU
On-chip clock oscillator
4K bytes of on-chip Program Memory-ROM
128 bytes of on-chip Data RAM
64KB Program Memory address space
64KB Data Memory address space
32 bidirectional I/0 lines (Port 0,1,2,3)
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
501
Two 16-bit timer/counters(Timer 1,Timer 0)
One serial port
UART(Universal Asynchronous Receiver Transmitter)
6-source interrupt structure
1. External interrupt INT0
2. Timer interrupt T0
3. External interrupt INT1
4. Timer interrupt T1
5. Serial communication interrupt
6. Timer Interrupt T2
4 Register Banks (Bank 0, Bank 1, Bank 2, Bank
3)
each bank has R0-R7 registers
502
Pin Description
of the 8051
503
504
I/O Port Pins
• The four 8-bit I/O ports
505
Port 3
• Port 3 can be used as input or output.
506
Pin Description Summary
PIN TYPE NAME AND FUNCTION
508
Architecture of
8051
microcontroller
509
510
511
512
External
External
60K
64K 64K
SFR
Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
518
Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
00-Bank 0
01-Bank 1
10-Bank 2
11-Bank 3
519
Data Pointer Register (DPTR)
It consists of two separate registers:
DPH (Data Pointer High) &
DPL (Data Pointer Low).
520
Stack Pointer (SP) Register
8 bit
8 bit
8 bit
8 bit
521
INSTRUCTION
SET OF
8051
522
8051 Instruction Set
• The instructions are grouped into 5 groups
– Arithmetic
– Logic
– Data Transfer
– Boolean
– Branching
523
1. Arithmetic Instructions
• ADD A, source
A A + <operand>.
• ADDC A, source
A A + <operand> + CY.
• SUBB A, source
A A - <operand> - CY{borrow}.
524
• INC
– Increment the operand by one. Ex: INC DPTR
• DEC
– Decrement the operand by one. Ex: DEC B
• MUL AB
Multiplication
A*B
Result
8 byte * 8 byte A=low byte,
B=high byte
• DIV AB
Division Quotient Remainder
8 byte /8 byte
A/B A B
525
Multiplication of Numbers
MUL AB ; A B, place 16-bit result in B
and A
A=07 , B=02
MUL AB ;07 * 02 = 000E where B = 00 and A = 0E
Division of Numbers
DIV AB ; A / B , 8-bit Quotient result in A &
8-bit Remainder result in B
A=07 , B=02
DIV AB ;07 / 02 = Quotient 03(A) Remainder 01 (B)
526
2. Logical
instructions
527
• ANL D,S
-Performs logical AND of destination & source
- Eg: ANL A,#0FH ANL A,R5
• ORL D,S
-Performs logical OR of destination & source
- Eg: ORL A,#28H ORL A,@R0
• XRL D,S
-Performs logical XOR of destination & source
- Eg: XRL A,#28H XRL A,@R0
528
• CPL A
-Compliment accumulator
-gives 1’s compliment of accumulator data
• RL A
-Rotate data of accumulator towards left without carry
• RLC A
- Rotate data of accumulator towards left with carry
• RR A
-Rotate data of accumulator towards right without carry
• RRC A
- Rotate data of accumulator towards right with carry
529
3. Data Transfer
Instructions
530
MOV Instruction
• MOV destination, source ; copy source to destination.
531
• MOVX
– Data transfer between the accumulator and
a byte from external data memory.
• MOVX A, @DPTR
• MOVX @DPTR, A
532
• PUSH / POP
– Push and Pop a data byte onto the stack.
• PUSH DPL
• POP 40H
533
• XCH
– Exchange accumulator and a byte variable
• XCH A, Rn
• XCH A, direct
• XCH A, @Ri
534
4.Boolean variable
instructions
535
CLR:
• The operation clears the specified bit indicated in
the instruction
• Ex: CLR C clear the carry
SETB:
• The operation sets the specified bit to 1.
CPL:
• The operation complements the specified bit
indicated in the instruction
536
• ANL C,<Source-bit>
• ORL C,<Source-bit>
537
• XORL C,<Source-bit>
• MOV P2.3,C
• MOV C,P3.3
• MOV P2.0,C
538
5. Branching
instructions
539
Jump Instructions
• LJMP (long jump):
– Original 8051 has only 4KB on-chip ROM
540
Call Instructions
• LCALL (long call):
– Target address within 64K-byte range
541
• 2 forms for the return instruction:
– Return from subroutine – RET
– Return from ISR – RETI
542
543
8051
Addressing
Modes
8051 Addressing Modes
• The CPU can access data in various ways, which are
called addressing modes
1. Immediate
2. Register
3. Direct
4. Indirect
5. Relative
6. Absolute
7. Long
8. Indexed
545
1. Immediate Addressing Mode
• The immediate data sign, “#”
• Data is provided as a part of instruction.
546
2. Register Addressing Mode
• In the Register Addressing mode, the instruction involves
transfer of information between registers.
547
3. Direct Addressing Mode
• This mode allows you to specify the operand by giving its
actual memory address
548
4. Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an
operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.
MOVX A,@DPTR
549
5. Relative Addressing
• This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
550
6. Absolute Addressing
• In Absolute Addressing mode, the absolute
address, to which the control is transferred, is
specified by a label.
• Two instructions associated with this mode
of addressing are ACALL and AJMP
instructions.
• These are 2-byte instructions
551
7. Long Addressing
• This mode of addressing is used with the
LCALL and LJMP instructions.
• It is a 3-byte instruction
• It allows use of the full 64K code space.
552
8. Indexed Addressing
• The Indexed addressing is useful when there is a
need to retrieve data from a look-up table (LUT).
553
8051
Assembly
Language
Programming(ALP)
554
ADDITION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS
9100: MOV A,#05
MOV B,#03
ADD A,B
MOV DPTR,#9200
MOVX @DPTR,A
HERE SJMP HERE
MUL AB DIV AB
UNIT-5
INTERFACING
MICROCONTROLLER
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
Velalar College of Engg & Tech ,
Erode
UNIT 5 Syllabus
• Programming 8051 Timers
• Serial Port Programming
• Interrupts Programming
• LCD & Keyboard Interfacing
• ADC, DAC & Sensor Interfacing
• External Memory Interface
• Stepper Motor & Waveform generation
560
8051
TIMERS
561
8051 Timer Modes
8051 TIMERS
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1 Mode 1
Mode 2 Mode 2
Mode 3
562
TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set(1), counter operation (input from Tx input pin).
When clear(0), timer operation (input from internal clock).
563
TMOD Register
00- MODE 0
01- MODE 1
10- MODE 2
11- MODE 3
564
TCON Register
OSC ÷12
C /T = 0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T =1
T PIN
INTERRUPT
TR
Gate
INT PIN
566
TIMER 0
OSC ÷12
C /T = 0
TL0 TH0 TF0
C /T =1
T 0 PIN
TR 0 INTERRUPT
Gate
INT 0 PIN
567
TIMER 0 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T = 0 TL0 TH0 INTERRUPT
TF0
(5 Bit) (8 Bit)
C /T =1
T 0 PIN
TR 0
Gate
INT 0 PIN
OSC ÷12
C /T = 0 TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)
C /T =1
T 0 PIN
TR 0
Gate
INT 0 PIN
OSC ÷12
C /T = 0 TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)
C /T =1
T 0 PIN
TR 0
Gate Reload
INT 0 PIN
TH0
(8 Bit)
OSC ÷12
C /T = 0 TL0 INTERRUPT
TF0
(8 Bit)
C /T =1
T 0 PIN
TR 0
Gate
INT 0 PIN
TR1
571
TIMER 1
OSC ÷12
C /T = 0
TL1 TH1 TF1
C /T =1
T 1PIN
INTERRUPT
TR1
Gate
INT1 PIN
572
TIMER 1 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T = 0 TL1 TH1 INTERRUPT
TF1
(5 Bit) (8 Bit)
C /T =1
T 1PIN
TR1
Gate
INT 1 PIN
OSC ÷12
C /T = 0 TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)
C /T =1
T 1PIN
TR1
Gate
INT 1 PIN
OSC ÷12
C /T = 0 TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)
C /T =1
T 1PIN
TR1
Gate Reload
INT 1 PIN
TH1
(8 Bit)
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
M_Nokhodchian @ yahoo.com Microprocessors 1-577
TCON Register (2/2)
• TF (timer flag, control flag)
– TF0 for timer/counter 0; TF1 for timer/counter 1.
– TF is like a carry. Originally, TF=0. When TH-TL roll
over to 0000 from FFFFH, the TF is set to 1.
• TF=0 : not reach
• TF=1: reach
• If we enable interrupt, TF=1 will trigger ISR.
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
M_Nokhodchian @ yahoo.com Microprocessors 1-578
Equivalent Instructions for the Timer Control Register
For timer 0
SETB TR0 = SETB TCON.4
CLR TR0 = CLR TCON.4
TF = 0 TF = 0 TF = 0 TF = 0 TF = 1
XTAL
oscillator 12 ÷
C/T = 0
Timer
overflow
flag
TH TL TF
TR
TF goes high when FFFF 0
(a) in hex
• (FFFF – YYXX + 1) × 1.085 s
• where YYXX are TH, TL initial values
respectively.
• Notice that values YYXX are in hex.
(b) in decimal
• Convert YYXX values of the TH, TL register to
decimal to get a NNNNN decimal number
• then (65536 – NNNNN) × 1.085 s
whole clock
Solution:
FFFFH – 7634H + 1 = 89CCH = 35276 clock
count
Half period = 35276 × 1.085 s = 38.274 ms
Whole period = 2 × 38.274 ms = 76.548 ms
Frequency = 1/ 76.548 ms = 13.064 Hz.
Note
Mode 1 is not auto reload then the program must
reload the TH1, TL1 register every timer overflow if we
want to have a continuous wave.
M_Nokhodchian @ yahoo.com Microprocessors 1-591
Find Timer Values
Solution:
1. The period of the square wave = 1 / 50 Hz = 20
ms.
2. The high or low portion of the square wave = 10
ms.
3. 10 ms / 1.085 s = 9216
4. 65536 – 9216 = 56320 in decimal = DC00H in
hex.
5. M_Nokhodchian
TL1 = 00H and TH1 = DCH.
@ yahoo.com Microprocessors 1-593
Example 3 (2/2)
MOV TH1,#0DCH
SETB TR1 ;start
BACK: JNB TF1,BACK
CLR TR1 ;stop
CPL P2.3
CLR TF1 ;clear timer flag 1
SJMP AGAIN ;reload timer since
;mode 1 is not
;auto-reload
M_Nokhodchian @ yahoo.com Microprocessors 1-594
8051
Serial
Port
595
596
Basics of Serial Communication
• Serial data communication uses two methods
– Synchronous method transfers a block of data at a time
597
598
599
Asynchronous – Start & Stop Bit
• Asynchronous serial data communication is widely used
for character-oriented transmissions
600
Asynchronous – Start & Stop Bit
601
Data Transfer Rate
• The rate of data transfer in serial data communication is
stated in bps (bits per second).
602
8051 Serial Port
• Synchronous and Asynchronous
• SCON Register is used to Control
• Data Transfer through TXd & RXd pins
• Some time - Clock through TXd Pin
• Four Modes of Operation:
603
Registers related to Serial
Communication
1. SBUF Register
2. SCON Register
3. PCON Register
604
SBUF Register
• SBUF is an 8-bit register used solely for serial communication.
• For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
• SBUF holds the byte of data when it is received by 8051 RxD
line.
605
SBUF Register
• Sample Program:
606
SCON Register
607
8051 Serial Port – Mode 0
The Serial Port in Mode-0 has the following features:
608
8051 Serial Port – Mode 1
The Serial Port in Mode-1 has the following features:
609
8051 Serial Port – Mode 2
The Serial Port in Mode-2 has the following features:
610
8051 Serial Port – Mode 3
The Serial Port in Mode-3 has the following features:
611
Programs in 8051 serial port
619
Interrupt
– Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing
and serves the device.
– The program which is associated with the
interrupt is called the interrupt service routine
(ISR) .
620
Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector
table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.
621
Steps in executing an interrupt
• Finish current instruction and saves the PC on stack.
624
8051 Interrupt related Registers
• The various registers associated with the use of
interrupts are:
– TCON - Edge and Type bits for External Interrupts 0/1
– IE - interrupt Enable
– IP - Interrupts priority
625
Enabling and Disabling an Interrupt
• The register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.
626
Interrupt Enable (IE) Register
--
• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.
MOV IE,#08h • ES : Enable Serial port interrupt.
or
SETB ET1 • ET1 : Enable Timer 1 control bit.
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.
627
Interrupt Priority
628
Interrupt Priority (IP) Register
Serial Port
Timer 1 Pin INT 0 Pin
KEYBOARD
INTERFACING
KEYBOARD INTERFACING
• Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
• Therefore, with two 8-bit ports, an 8 x 8
matrix of keys can be connected to a
microprocessor
When a key is pressed, a row and a
column make a contact
632
• Otherwise, there is no connection
between rows and columns
• A 4x4 matrix connected to two ports
The rows are connected to an
output port and the columns are
connected to an input port
633
4x4 matrix
634
635
Connection with keyboard matrix
Final Circuit
Stepper Motor
Interfacing
638
Stepper Motor Interfacing
• Stepper motor is used in applications such as;
dot matrix printer, robotics etc
639
640
641
Full step
642
Step angle:
• Step angle is defined as the minimum degree of rotation
with a single step.
• No of steps per revolution = 360° / step angle
• Steps per second = (rpm x steps per revolution) / 60
• Example: step angle = 2°
• No of steps per revolution = 180
643
A switch is connected to pin P2.7. Write an ALP to
monitor the status of the SW.
If SW = 0, motor moves clockwise and
If SW = 1, motor moves anticlockwise
SETB P2.7
MOV A, #66H
MOV P1,A
TURN: JNB P2.7, CW
RL A
ACALL DELAY
MOV P1,A DELAY: MOV R1,#20
L2: MOV R2,#50
SJMP TURN
L1:DJNZ R2,L2
CW: RR A DJNZ R2,L1
ACALL DELAY RET
MOV P1,A
644
SJMP TURN
LCD Interfacing
{before discussed in Unit 3 LCD
interfacing using 8086}
645
646
Pin Connections of LCD:
647
648
A/D Interfacing
{before discussed in Unit 3 A/D
interfacing using 8086}
649
Interfacing ADC to 8051
ADC0804 is an 8 bit successive approximation analogue to digital
converter from National semiconductors. The features of ADC0804 are
differential analogue voltage inputs, 0-5V input voltage range, no zero
adjustment, built in clock generator, reference voltage can be externally
adjusted to convert smaller analogue voltage span to 8 bit resolution etc.
650
ADC Interfacing:
651
D/A Interfacing
{before discussed in Unit 3 D/A
interfacing using 8086}
652
8051 Connection to DAC808
653
program to send data to the DAC to generate
a stair-step ramp
654
SENSOR
INTERFACING
take temperature sensor for example
655
8051 WITH TEMPERATURE
SENSOR
656
potentiometer
Shunt voltage
diodes
657
EXTERNAL
MEMORY
INTERFACING
658
Access to External Memory
• Port 0 acts as a multiplexed address/data bus. Sending
the low byte of the program counter (PCL) as an
address.
• Port 2 sends the program counter high byte (PCH)
directly to the external memory.
• The signal ALE operates as in the 8051 to allow an
external latch to store the PCL byte while the multiplexed
bus is made ready to receive the code byte from the
external memory.
• Port 0 then switches function and becomes the data bus
receiving the byte from memory.
659
660
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode