CoreGPIO

Features
APB2, APB3 support
8-, 16-, or 32-bit APB data width
1 to 32 bits of I/O for all APB-width configurations
• Fixed or configurable interrupt generation:
• Negative edge
• Positive edge
• Both edges
• Level high
• Level low
• Parameter-configurable for single-interrupt signal or up to 32-bit wide interrupt bus
• Fixed or configurable I/O type (input, output, or both)
• Configurable output enable (internal or external implementation)
Functional Block Diagram

this is replicated up to 32 times, depending on the number of I/Os).

Generics
• If “Output Enable” is external, then
when GPIO_OE is 0 output is high
impedance (Z)

• Selecting one type for options will

optimize out ports/registers for other
types.
• If I choose only input, then
GPIO_OUT will be synthesized
out.
Register Map
Register sizes vary with register
APB data width.
Configuration Registers