Introduction

to CMOS Transistor and

Transistor Fundamental
 Introduction
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): very many
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip

0: Introduction CMOS VLSI Design Slide 2

 Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

0: Introduction CMOS VLSI Design Slide 3

 Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

0: Introduction CMOS VLSI Design Slide 4

 p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

0: Introduction CMOS VLSI Design Slide 5

 nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+

p bulk Si

0: Introduction CMOS VLSI Design Slide 6

 nMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design Slide 7

 nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design Slide 8

 pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

0: Introduction CMOS VLSI Design Slide 9

 Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0: Introduction CMOS VLSI Design Slide 10

 Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

0: Introduction CMOS VLSI Design Slide 11

 Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

0: Introduction CMOS VLSI Design Slide 12

 Series and Parallel

a a a a
nMOS: 1 = ON g1
a
0 0 1 1


g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

 Series: both must be ON a a a a a

 Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

0: Introduction CMOS VLSI Design Slide 13

 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
0: Introduction CMOS VLSI Design Slide 14
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
0: Introduction CMOS VLSI Design Slide 15
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
0: Introduction CMOS VLSI Design Slide 16
 CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

0: Introduction CMOS VLSI Design Slide 17

 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

0: Introduction CMOS VLSI Design Slide 18

 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

0: Introduction CMOS VLSI Design Slide 19

 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

0: Introduction CMOS VLSI Design Slide 20

 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

0: Introduction CMOS VLSI Design Slide 21

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

0: Introduction CMOS VLSI Design Slide 22

 3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

0: Introduction CMOS VLSI Design Slide 23

 3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction CMOS VLSI Design Slide 24