CS321 Computer Architecture

8085 Architecture &
Its Assembly language programming

Outline
• 8085 Era and Features
• 8085
– Block diagram (Data Path)
– Bus Structure
– Register Structure
• Instruction Set of 8085
• Sample program of 8085
8085 Microprocessor
• 8 Bit CPU
• 3-6Mhz
• Simpler design
• ISA = Pre x86 design (Semi CISC)
• 40 Pin Dual line Package
• 16 bit address
• 6 registers: B, C, D, E, H,L
• Accumulator 8 bit
Pin-diagram
Functional block diagram
8085 Microprocessor Architecture
RST6.5
INTR INTA RST5.5 RST7.5 TRAP SID SOD
Interrupt Control Serial I/O Control
Bus 8 Bit
MUX
ACC tmp R
IR W Z
B C
Flag
I Decode D E
& H L
M/C
ALU Encodin
SP
g PC
Inc/Dec. ter
Add latch
Timing and Control Add Buf Data/Add Buf

The 8085 Bus Structure
A15
Address Bus (16bit)
A0
Memory I/P
8085
MPU
O/P
D7
Data Bus (8bit)
D0
Control Bus (8bit)

8085 Bus Structure
• Address Bus : Consists of 16 address lines: A0 – A15
– Address locations: 0000 (hex) – FFFF (hex)
– Can access 64K ( = 216 ) bytes of memory, each byte has 8 bits
– Can access 64K  8 bits of memory
– Use memory to map I/O, Same instructions to use for accessing
I/O devices and memory
• Data Bus : Consists of 8 data lines: D0 – D7
– Operates in bidirectional mode
– The data bits are sent from the MPU to I/O & vice versa
– Data range: 00 (hex) – FF (hex)
• Control Bus:
– Consists of various lines carrying the control signals such as
read / write enable, flag bits
8085 Registers
• Registers:
– Six general purpose 8-bit registers: B, C, D, E, H,L
– Combined as register pairs to perform 16-bit
operations: BC, DE, HL
– Registers are programmable (load, move, etc.)
• Stack Pointer (SP) B C
D E
• Accumulator & Flag Register H L
SP
– (Zero, Sign, Carry, Parity, AuxCarry)
PC
• Program Counter (PC)
– Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Register Addressing
• The most common form of data addressing.
– once register names learned, easiest to apply.
• The microprocessor contains these 8-bit register
names used with register addressing: AH, AL, BH,
BL, CH, CL, DH, and DL.
• 16-bit register names: AX, BX, CX, DX, SP, BP, SI,
and DI.
• In 80386 & above, extended 32-bit register names
are: EAX, EBX, ECX, EDX, ESP, EBP, EDI, and ESI.
• 64-bit mode register names are: RAX, RBX, RCX,
RDX, RSP, RBP, RDI, RSI, and R8 through R15.
• Important for instructions to use registers that are
the same size.
– never mix an 8-bit with a 16-bit register, an 8- or a 16-
bit register with a 32-bit register
– this is not allowed by the microprocessor and results
in an error when assembled
Flag Register
Status Signals
IO/M S1 S0 OPERATION
0 1 1 Opcode fetch
0 1 0 Memory read
0 0 1 Memory write
1 1 0 I/O read
1 0 1 I/O write
Interrupt
1 1 0 acknowledge
Z 0 1 Halt
Z x x Hold
Z x x Reset
Reset Signal
• RESET IN : When this signal goes low,
– the program counter (PC) is set to Zero,
– μp is reset
– The data and address buses and the control lines are 3-stated
during RESET
– The CPU is held in the reset condition as long as RESET- IN is
applied
• RESET OUT: This signal indicates that μp is being reset.
– This signal can be used to reset other devices.
– The signal is synchronized to the processor clock and lasts an
integral number of clock periods.
–.
Serial communication
• Serial communication Signal

– SID - Serial Input Data Line: The data on this line
is loaded into accumulator bit 7 whenever a RIM
instruction is executed.
– SOD – Serial Output Data Line: The SIM
instruction loads the value of bit 7 of the
accumulator into SOD latch if bit 6 (SOE) of the
accumulator is 1.
DMA Signals
• HOLD: Indicates that another master is requesting the use of the
address and data buses.
– The CPU, upon receiving the hold request, will relinquish the use of the bus as
soon as the completion of the current bus transfer.
– Internal processing can continue. The processor can regain the bus only after the
HOLD is removed.
– When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are
3-stated.
• HLDA: Hold Acknowledge: Indicates that the CPU has received the
HOLD request and that it will relinquish the bus in the next clock cycle.
– HLDA goes low after the Hold request is removed. The CPU takes the bus one
half-clock cycle after HLDA goes low.
Ready Signal
• READY: This signal Synchronizes the fast CPU and the
slow memory, peripherals.
• If READY is high during a read or write cycle, it
indicates that the memory or peripheral is ready to
send or receive data.
• If READY is low, the CPU will wait an integral number
of clock cycle for READY to go high before completing
the read or write cycle.
• READY must conform to specified setup and hold
times.
Interrupts
• 8085 has 5 interrupts priority (from lowest to highest):
• INTR: (maskable and non-vectored interrupt). When the interrupt occurs, the processor fetches from the bus
one instruction, usually one of these instructions:
– One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to
memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
– CALL: (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of
the instruction.
• RST5.5: (maskable interrupt). When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 2CH address.
• RST6.5: (maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 34H address
• RST7.5 (maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 3CH (hexadecimal) address
• TRAP: (non-maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 24H address.
• All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5
interrupts can be enabled or disabled individually using SIM instruction
8085 Non-Vectored Interrupt Process
• The interrupt process should be enabled using the EI instruction.
• The 8085 checks for an interrupt during the execution of every instruction.
• If INTR is high, Processor completes current instruction, disables the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that interrupted
• INTA allows the I/O device to send a RST instruction through data bus.
• MP saves the memory location of the next instruction, on the stack and the
program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
• Microprocessor Performs the ISR. ISR must include the ‘EI’ instruction to enable
the further interrupt within the program.
• RET instruction at the end of the ISR allows the MP to retrieve the return
address from the stack and the program is transferred back to where the
program was interrupted.
Interrupt vectors
• An interrupt vector is a pointer to where the ISR is stored in
memory.
• All interrupts (vectored or otherwise) are mapped onto a memory
area called the Interrupt Vector Table(IVT).
• The IVT is usually located in memory page 00 (0000H - 00FFH).
• Example:
– Let a device interrupts the Microprocessor using the RST 7.5 interrupt line.
– Because the RST 7.5 interrupt is vectored, Microprocessor knows in which
memory location it has to go using a call instruction to get the ISR address.
– RST7.5 is known as Call 003Ch to Microprocessor. Microprocessor goes to
003C location and will get a JMP instruction to the actual ISR address. The
microprocessor will then, jump to the ISR location
Vectored Interrupt
• The interrupt process should be enabled using the EI instruction.
• The 8085 checks for an interrupt during the execution of every
instruction.
• If there is an interrupt, and if the interrupt is enabled using the
interrupt mask, the microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
• The microprocessor then executes a call instruction that sends the
execution to the appropriate location in the interrupt vector table.
• When the microprocessor executes the call instruction, it saves the
address of the next instruction on the stack.
• The microprocessor jumps to the specific service routine.
• The service routine must include the instruction EI to re-enable the
interrupt process.
• At the end of the service routine, the RET instruction returns the
execution to where the program was interrupted.
MANIPULATING THE MASKS
• MANIPULATING THE MASKS

– The Interrupt Enable flip flop is manipulated using the
EI/DI instructions.
– The individual masks for RST 5.5, RST 6.5 and RST 7.5
are manipulated using the SIM instruction.
– The SIM instruction takes the bit pattern in the

Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.
How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0
M7.5
M5.5
M6.5
MSE
SDO
R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to SOD pin 1 - Set the masks according
to bits 0-2
Not Used Force RST7.5 Flip Flop to reset
If MSE is 1
If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.
23
How RIM sets the Accumulator’s different bits
7 6 5 4 3 2 1 0
M7.5
M5.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
}
RST5.5 Mask
Serial Data In 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop
Determining the Current Mask Settings
• RIM instruction: Read Interrupt Mask
– Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and
mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
P7.5
P6.5
P5.5
SDI
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
Flip Flop
25
What is Memory Mapped I/O?
• Instead of having special methods for accessing
the values to be read or written, just get them
from memory or put them into memory.
• The device is connected directly to certain main
memory locations.
• Two types of information to/from the device
– Status
– Value read/write
Memory Mapped I/O
CPU
Address
Data
7 0
Main memory
Data register
(address = 5000)
7 0
Ready IF … IE Status register

(address = 5002)
Keyboard controller
Mother Board
comparison
Memory mapping I/O mapping
16/20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for I/O
devices
The I/O ports or peripherals can be treated like Only IN and OUT instructions can be used for data
memory locations and so all instructions related transfer between I/O device and processor
to memory can be used for data transmission
between I/O device and processor
Data can be moved from any register to ports Data transfer takes place only between
and vice versa accumulator and ports
When memory mapping is used for I/O devices, Full memory space can be used for addressing
full memory address space cannot be used for memory.
addressing memory.
 Suitable for systems which require large
 Useful only for small systems where memory memory capacity
requirement is less
For accessing the memory mapped devices, the For accessing the I/O mapped devices, the
processor executes memory read or write cycle. processor executes I/O read or write cycle.
 M / is asserted high  M / is asserted low

29
IO Mapped IO Device I/O Port Locations on PCs (partial)
Instruction format
• Based on word size(8-bit processor so byte is same as word)
– One byte instruction
– Ex.: Mov rd,rs
• Binary code: 01 ddd sss
• Mov A,B: 01 111 000 = 78h
– Two byte instruction
– Ex.: mvi A, data
• Binary code: 0011 1110 data
• Mvi A, 30: 3E 30h
– Three byte instruction
– Ex.: Lxi rp,data_address //rp: register pair
– Binary code: 21 lower_byte upper byte address
– Lxi H, 2236: 21 36 22 h
MACHINE CYCLE
 The 8085 CPU can perform seven basic machine
operations. All but the bus-idle cycle involve the transfer of
data between the CPU and a peripheral device.
 The seven machine cycles are :
•Opcode Fetch fetch the opcode of an instruction from
memory
•Memory Read read data stored at an addressed memory
location
•Memory Write write data to an addressed memory location
•IO Read read data from an addressed input device
•IO Write write data to an addressed output device
•Interrupt Ack acknowledge an interrupt request
•Bus Idle no bus operation
MACHINE CYCLE
• Example instruction: STA addr
T-STATE
 The operation of the 8085 can be described with
respect to its state diagram ( it is a synchronous state
machine )
MACHINE CYCLE
• Opcode Fetch
– The first operation in every instruction
– Retrieves the opcode of the instruction that is being
executed
– Usually composed 4 clock cycles (T-state)
– Some instruction required 6 T-state (CALL, INX, DCX)
– IO/M signal is low (indicating a memory operation)
MACHINE CYCLE
 Memory Read
– Machine cycle during which memory is read
– Composed 3 clock cycles
 Memory Write
– This machine cycle is used when the 8085 needs to send data
out from the accumulator or a specific register and then write it
into memory
MACHINE CYCLE
 I/O Read
– Indicates that data is being read from an I/O device
– Occurs when IN instruction is executed
– IO/M signal is high (indicating an I/O operation)
 I/O Write
– This machine cycle is used to write data out from accumulator in the
microprocessor to the I/O device specified by the port address
– Occurs when OUT instruction is executed
– IO/M signal is high (indicating an I/O operation)
MACHINE CYCLE
• Interrupt Acknowledge
– Special machine cycle that is used to place of the
opcode fetch cycle in the RST (restart) instruction.
– Similar to opcode fecth instruction except that it send
out INTA signal instead of RD signal and IO/M signal is
High
– Composed 6 clock cycle
T-STATE
• Key to timing diagram
Indicates a bus. Whilst the lines remain parallel the
individual bits of the bus remain unchanged.
Indicates a bus. Where the lines cross indicates a
possible change in logic level of one or more bits of the
bus.
Indicates a 0 -> 1 transition of a digital signal
Indicates a 1 -> 0 transition of a digital signal
Indicates a bus or a bit being in the Hi-Z state ( tri-

state )
The tail of the arrow indicates the cause of a signal
change.
The head of the arrow indicates the affected signal.
Opcode Fetch
MVI
STA 526A
(32, 6A, 52 ( ACC-C7)
Wait-State
Instruction Set & Addressing mode
• Instruction Set:
– 8085 instruction set consists of the following instructions:
– Data moving instructions.
– Arithmetic - add, subtract, increment and decrement.
– Logic - AND, OR, XOR and rotate.
– Control transfer - conditional, unconditional, call subroutine, return from subroutine and
restarts.
– Input/Output instructions.
– Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
• Addressing mode
– Register - references the data in a register or in a register pair.
– Register indirect - instruction specifies register pair containing address, where the data is
located.
– Direct,
– Immediate - 8 or 16-bit data
8085 Microprocessor Memory
• Memory:
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64KB.
• Program memory - program can be located anywhere in memory.

– Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB.
– All jump/ branch instructions use absolute addressing.
• Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
• Stack memory is limited only by the size of memory. Stack grows downward.
• First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions
8085 MP Instruction Set Architecture
• Contains several registers include B,C,D,E,H,L and an 8-bit
accumulator register, A.
• The registers B,C,D,E,H,L can be accessed as pairs. Pairs are not
arbitrary. B and C, D and E, H and L.
• SP is a 16 bit stack pointer register pointing to the top of the stack.
• PC is a 16-bit Program counter
• Contains five flags known as flag registers:
Instruction Set of 8085
• Arithmetic Operations
– add, sub, inr/dcr
• Logical operation
– and, or, xor, rotate, compare, complement
• Branch operation
– Jump, call, return
• Data transfer/Copy/Memory operation/IO
– MOV, MVI, LD, ST, OUT
Copy/Mem/IO operation
• MVI R, 8 bit // load immediate data
• MOV R1, R2 // Example MOV B, A
• MOV R M // Copy to R from 0(HL Reg) Mem
• MOV M R // Copy from R to 0(HL Reg) Mem
• LDA 16 bit // load A from 0(16bit)

• STA 16 bit // Store A to 0(16bit)
• LDAX Rp // load A from 0(Rp), Rp=RegPair
• STAX Rp // Store A to 0(Rp)
• LXI Rp 16bit // load immediate to Rp
• IN 8bit // Accept data to A from port 0(8bit)

• OUT 8 bit // Send data of A to port 0(8bit)
Arithmetic Operation
• ADD R // Add A = A + B.reg
• ADI 8bit // Add A= A + 8bit
• ADD M // Add A=A + 0(HL)
• SUB R // Sub A = A -B.reg

• SUI 8bit // Sub A= A - 8bit
• SUB M // Sub A=A - 0(HL)
• INR R // R = R+1
• INR M // 0(HL)=0(HL)+1
• DCR R // R = R-1
• DCR M // 0(HL)=0(HL)-1
• INX Rp // Rp=Rp+1
• DCX Rp // Rp=Rp-1
Other Operations
• Logic operations
– ANA R ANI 8bit ANA M
– ORA, ORI, XRA, XRI
– CMP R // compare with R with ACC
– CPI 8bit // compare 8 bit with ACC
• Branch operations
– JMP 16bit, CALL 16 bit
– JZ 16bit, JNZ 16bit, JC 16bit, JNC 16 bit
– RET
• Machine Control operations
– HLT, NOP, POP, PUSH
8085 Microprocessor Instruction Set
Contains a total of 74 different instructions.

R, R1, R2 8 bit registers representing A, B, C, D, E, H or L
M Indicates memory location
RP Indicates register pair such as BC, DE, HL, SP
 16 bit address representing address or data value.
n 8-bit address or data value stored in memory immediately after the

opcode
Cond Condition for conditional instructions. NZ (Z = 0), Z (Z =

1),P (S = 0), N (S = 1), PO (P = 0), PE (P = 1), NC (CY = 0),
C (CY=1)
Data movement instruction for the 8085 microprocessor
Instruction Operation
NOP No operation
MOV r1, r2 r1 = r2
MOV r, M r1 = M[HL]
MOV M, r M[HL] = r
MVI r, n r=n
MVI M, n M[HL] = n
LXI rp,  rp = 
LDA  A = M[]
STA  M[] = A
LHLD  HL = M[], M[ + 1]
SHLD  M[], M[ + 1] = HL
LDAX rp A = M[rp] (rp = BC, DE)
STAX rp M[rp] = A (rp = BC, DE)
XCHG DE  HL
PUSH rp Stack = rp (rp  SP)
PUSH PSW Stack = A, flag register
POP rp rp = Stack (rp  SP)
POP PSW A, flag register = Stack
XTHL HL  Stack
SPHL SP = HL
IN n A = input port n
OUT n Output port n = A
Data operation instruction for the 8085 microprocessor
Instruction Operation Flags
ADD r A=A+ r All
ADD M A = A + M[HL] All
ADI n A=A+ n All
ADC r A = A + r + CY All
ADC M A = A + M[HL] + CY All
ACI n A = A + n + CY All
SUB r A=A- r All
SUB M A = A - M[HL] All
SUI n A=A- n All
SBB r A = A - r - CY All
SBB M A = A - M[HL] - CY All
SBI n A = A - n - CY All
INR r r=r+1 Not CY
INR M M[HL] = M[HL] + 1 Not CY
DCR r r=r-1 Not CY
DCR M M[HL] = M[HL] - 1 Not CY
INX rp rp = rp + 1 None
DCX rp rp = rp - 1 None
DAD rp HL = HL + rp CY
DAA Decimal adjust All
ANA r A=A r All
ANA M A = A  M[HL] All
Data operation instruction for the 8085 microprocessor
Instruction Operation Flags

ANI n A=A n All
ORA r A=A r All
ORA M A = A  M[HL] All
ORI n A=A n All
XRA r A=A r All
XRA M A = A  M[HL] All
XRI n A=A n All
CMP r Compare A and r All
CMP M Compare A and M[HL] All
CPI n Compare A and n All
RLC CY = A7, A = A(6-0), A7 CY
RRC CY = A0, A = A0, A(7-1) CY
RAL CY, A = A, CY CY
RAR A, CY = CY, A CY
CMA A = A’ None
CMC CY = CY’ CY
STC CY = 1 CY
Program control instruction
Instruction Operation
JUMP  GOTO 
J cond  If condition is true then GOTO 
PCHL GOTO address HL
CALL  Call subroutine at 
C cond  If condition is true then call subroutine at 
RET Return from subroutine
R cond If condition is true then return from
subroutine
RST n Call subroutine at 8*n (n = 5.5, 6.5, 7.5)
RIM A = IM
SIM IM = A
DI Disable interrupts
EI Enable interrupts
HLT Halt the CPU
A Simple 8085 Program
1: i = n, sum = 0
2: sum = sum + i, i = i - 1
3: IF i  0 then GOTO 2
4: total = sum
A Simple 8085 Program (contd)
LDA n
i=n
MOV B, A
XRA A sum = A  A = 0
Loop: ADD B sum = sum + i
DCR B i=i-1
JNZ Loop IF i  0 THEN GOTO Loop
STA total total = sum

Execution trace
Instruction 1st Loop 2nd Loop 3rd Loop 4th Loop 5th Loop
LDA n B=5
MOV B, A
XRA A A= 0
ADD B A= 5 A= 9 A = 12 A = 14 A = 15
DCR B B = 4, B = 3, B = 2, B = 1, B = 0,
Z=0 Z=0 Z=0 Z=0 Z=1
JNZ Loop JUMP JUMP JUMP JUMP NO JUMP
STA total total = 15

Simple Assembly Program
MVI A, 24H // load Reg ACC with 24H
MVI B , 56H // load Reg B with 56H
ADD B // ACC= ACC+B
OUT 01H // Display ACC contents on port 01H
HALT // End the program
Result: 7A (All are in Hex)

Code to multiply two number
LDA 2000 // Load multiplicant to accumulator
MOV B,A // Move multiplicant from A(acc) to B register
LDA 2001 // Load multiplier to accumulator
MOV C,A // Move multiplier from A to C
MVI A,00 // Load immediate value 00 to a
L: ADD B // Add B(multiplier) with A
DCR C // Decrement C, it act as a counter
JNZ L // Jump to L if C reaches 0
STA 2010 // Store result in to memory
HLT // End
|
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Next…
• 8086
– Block diagram (Data Path), Registers
• Memory Model
– Stack, Data and Code Segment
• Instruction Set of x86
• Addressing mode
• Procedure and subroutine
• Examples programs in C/C++ assembly
• Peripheral device and Assembly program
8086 Architecture
Bus Interface
C BUS
Unit
SUM Q6
Q5
Q4
Q3
Q2
Q1
CS (Code Seg Reg)

DS (Data Seg Reg )
ES (Extra Seg Reg )
SS (Stack Seg Reg)
IP (Intr Ptr)
Operand
InDirect
Sequencer
Execution
A BUS
Unit
AH AL Temp A
BH BL Temp B
CH CL Temp C
DH DL
SI (Source Idx )
DI (Dest. Idx)
BP (Base Ptr ) ALU
SP (Stack Ptr)
Z (Flag Reg)
Minimum/Max Mode Configuration For 8086
The microprocessor 8086 is operated in minimum mode

by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by

the microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
In the maximum mode, the 8086 is operated by

strapping the MN/MX pin to ground.
In the maximum mode, there may be more than one

microprocessor in the system configuration. The
components in the system are same as in the minimum
mode system.
8086 & x86 Registers
31 15 7 0
• AX - accumulator reg EAX AH AL
• BX - base address reg EBX BH BL
ECX CH CL
• CX - count reg EDX DH DL
• DX - data reg ESI SI (Source Idx )
EDI DI (Dest. Idx)
• SI - source index reg EBP BP (Base Ptr )
• DI - dest index reg ESP SP (Stack Ptr)
• BP - base pointer. EZ Z (Flag Reg)
• SP - stack pointer. ECS CS (Code Seg Reg)
EDS DS (Data Seg Reg )
EES ES (Extra Seg Reg )
ESS SS (Stack Seg Reg)
EIP IP (Intr Ptr)

Memory layout of C program
int A;
Stack
int B=10;
main(){
Heap
int Alocal;
int *p; BSS
p=(int*)malloc(10); Data
}
Code
Memory layout of C program
• Stack
– automatic (default), local Stack
– Initialized/uninitialized
• Data
Heap
– Global, static, extern
– BSS: Block Started by Symbol BSS
• Code
– program instructions Data
• Heap
– malloc, calloc
Code
8086
Microprocessor Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
69
Main
Code and
Memory
if (j>k) Code_Segment: Data
0000
segments Operating
max = mov AX, [0]
are separate System
j mov BX, [2] and both
(Kernel)
assumed
else cmp AX,BX to start 0700
max = from 0
jle 0x7 //Label_1 Other User
k Every Memory
Process
mov [4], AX Data
Access should
add 0900
jmp 0x5 //Label_2
the value stored
in Our Code
Label_1: mov [4], BX Data Segment
Register Segment
By default.
Label_2: ….
Segment Register 1900
(Data) Vacant
Data Segment: 2100
Address of j: Space
2100 0: // Allocated for j 2100
Address of k:
2102 2: // Allocated for k Our Data
Address of max:
2104
Segment
4: // Allocated for 2300
max Vacant
Space
2500
Ease Of Programming
Main Memory
0000
if (j>k) Code_Segment:
max = j mov AX, [0]
Operating System
else (Kernel)
mov BX, [4]
max = k
cmp AX,BX 0700
jle 0x7 //Label_1

Other User
mov [4], AX A new process Process
needs a
jmp 0x5 //Label_2 segment of size 0900
260
The space is
Label_1: mov [4], BX available Our Code
but not contiguous Segment
Label_2: ….
Segment Register 1900
(Data)
Address of j:
Data Segment: 2100
2300 Vacant
New
Space
User
2100
Address of k: 0: // Allocated for j 2100
Process
2102
Address of 2: // Allocated for k Our
Vacant
Data
2160
max: 2104 Segment
Space
Vacant Space
4: // Allocated for max 2300
Address of j:
Our
Vacant
Data
2300
Segment
Space
Address of k:
2302 2500
Address of Process Mobility
max: 2304
Multiple Segments
• The segment register can change its values to point to

different segments at different times.
• X86 architecture provides additional segment registers to
access multi data segments at the same time.
– DS, ES, FS and GS
• X86 supports a separate Stack Segment Register (SS) and a
Code segment Register (CS) in addition.
• By default a segment register is fixed for every instruction,
for all the memory access performed by it. For eg. all data
accessed by MOV instruction take DS as the default segment
register.
• An segment override prefix is attached to an instruction to
change the segment register it uses for memory data access.
0000
mov [10], ax
- this will move the DS

contents of ax register to
memory location 0510
0500
Opcode: 0x89 0x05 0x10
mov [ES:10], ax
-this will move the contents
of ax register to memory 1500
location 3510 CS
Opcode
0x26 0x89 0x05 0x10
“0x26” is the segment SS 2500

override prefix.
3500
ES
Multiple Segments
Process 1
CS
CS
Process 1
DS
Process 1 in
Execution Process 2
DS
CS
Process 2
SS
SS Process 2
DS
Process 2
in Process 1
SS
Execution
Multiprocess Context switching

• Three salient features of using
Segmentation
 Three Features
 Code Mobility
 Logically every segment can start
with zero
 Inter and Intra process protection
ensuring data integrity.
Real Mode - Memory Addressing
•Segment << 4 + offset = 20 bit EA
•Segment size is a fixed 64K

mov [0x1000], AX
DS = 0x1004
The mov will store the content of AX in
0x10040 + 0x1000 = 0x11040
Why this stuff? - To get 1 MB addressing using 16-bit

Segment Registers
•A process always executes from Code segment. It should not
execute by accessing from adjoining Data or stack area or any
other code area too.
•A stack should not overgrow into adjoining segments
500
CS
Every segment is specified a
1000 start address and limit.
ES Architecture checks if limit is

1500 not exceeded.
SS 2000
jmpmov
PUSH[ES:499],
CS:501 AX //Let
//This AXSP
is //This
a be 499,
violation is a as
POP
PUSH
movAX
jmp
POPAX //Let
CS:250
[ES:498],
AX//Let
//Let SP
SP
SPbe
AX be
be0,
//This Violation!!!
is itfine
//This
498,
2, it
is
isis
fine
fine
fine
violation!!!
violation
limit is 500
Intra and Inter process Protection

Process 1 should Process 1
be prevented CS
from loading CS, C
such that it can S Process 1
access the code of DS
Process 2 D Process 2
Similarly for the S CS
DS,SS, ES, FS and Process 2
GS SS
S
Process 2
S DS
Privilege levels:
[0-3] assigned to Process 1
each segment. SS
0: Highest
privilege
3: Lowest
privilege Interprocess Protection
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Dedicated Adder to
generate 20 bit address
Four 16-bit segment

registers
Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 79

8086
Microprocessor
Segment Code Segment Register

Registers
16-bit
CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.
80
8086
Microprocessor
Segment Data Segment Register

Registers
16-bit
Points to the current data segment; operands for most

instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.
81
8086
Microprocessor
Segment Stack Segment Register

Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).
82
8086
Microprocessor
Segment Extra Segment Register

Registers
16-bit
Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-

bit physical address for the destination.
83
8086
Microprocessor
Segment Instruction Pointer

Registers
16-bit
Always points to the next instruction to be executed

within the currently executing code segment.
So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution

of the next instruction takes place.
84
8086
Microprocessor
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.
This mechanism is known

as pipelining.
85
8086
Architecture Execution Unit (EU)
Microprocessor
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for

performing arithmetic
and logic operation
Four general purpose

registers(AX, BX, CX, DX);
Pointer registers (Stack

Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 86
DX can be used as DH and DL
8086
Microprocessor
EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,

and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or

AL.
87
8086
Microprocessor
EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.
This is the only general purpose register whose contents

can be used for addressing the 8086 memory.
All memory references utilizing this register content for

addressing use DS as the default segment register.
88
8086
Microprocessor
EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
89
8086
Microprocessor
EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 16 division and the 16-bit reminder after division.
90
8086
Microprocessor
EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.
91
8086
Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
92
8086
Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
93
8086
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 94
8086
Microprocessor Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
groups OF DF IF TF SF ZF AF PF CF
Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register

95
8086
Microprocessor Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations
BX Base register Used to hold base value in base addressing mode

to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions
DX Data Register Used to hold data for multiplication and division

operations
SP Stack Pointer Used to hold the offset address of top stack

memory
BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)

for string instructions
DI Data Index Used to hold the index value of destination

operand (data) for string operations 96
ADDRESSING MODES
&
Instruction set
8086
Microprocessor Introduction
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
High Level Low Level
Machine Language Assembly Language
 Binary bits  English Alphabets

 ‘Mnemonics’
 Assembler
Mnemonics  Machine
Language 98
ADDRESSING MODES
8086
Microprocessor Addressing Modes
Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports
11. Relative Addressing Group IV : Relative Addressing mode
12. Implied Addressing Group V : Implied Addressing mode

100
8086 Group I : Addressing modes for
Microprocessor Addressing Modes register and immediate data
1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL
7. Based Index Addressing (CL)  (DH)
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
101
8086 Group I : Addressing modes for
Microprocessor Addressing Modes register and immediate data
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
Example:
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
7. Based Index Addressing (DL)  08H

MOV AX, 0A9FH
10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
(AX)  0A9FH
102
8086
Microprocessor Addressing Modes : Memory Access
20 Address lines  8086 can address up to

220 = 1M bytes of memory
However, the largest register is only 16 bits
Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.
Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)
Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
104
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
2. Immediate Addressing
Here, the effective address of the memory
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
106
1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.
3. Direct Addressing Registers used to hold EA are any of the following

registers:
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
address calculation.
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
107
1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.
5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
used.
Example:
MOV AX, [BX + 08H]
Operations:
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA) 108

(AH)  (MA + 1)
1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.
5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.

Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA + 1)
109
1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
Example:
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
000AH  0AH (Sign extended)
8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
10. Indirect I/O port Addressing (DX)  (MA) or,
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)
110
1. Register Addressing Employed in string operations to operate on string

data.
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored
in DI register.
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES

Example: MOVS BYTE
Operations:
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA
11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI)
111+ 1
8086 Group III : Addressing
Microprocessor Addressing Modes modes for I/O ports
1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]
5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
7. Based Index Addressing Content of port with address 09H is

moved to AL register
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port

whose address is specified by DX
register. 112
8086 Group IV : Relative
Microprocessor Addressing Modes Addressing mode
3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
Operations:
8. String Addressing 000AH  0AH (sign extend)
9. Direct I/O port Addressing If ZF = 1, then
10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to
new address calculated above.
If ZF = 0, then next instruction of the

program is executed.
113
8086 Group IV : Implied
Microprocessor Addressing Modes Addressing mode
5. Based Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
operated by the instruction.
Example: CLC
This clears the carry flag to zero.
114
INSTRUCTION SET
8086
Microprocessor Instruction Set
8086 supports 6 types of instructions.
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
116
8086
Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.
Generally involve two operands: Source operand and

Destination operand of the same size.
Source: Register or a memory location or an immediate data

Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.
117
8086
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)
MOV reg/ mem, data
MOV reg, data (reg)  data

MOV mem, data (mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)
118
8086
PUSH reg16/ mem
PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg16/ mem
POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2 119
8086
IN A, [DX] OUT [DX], A
IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)
IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)
IN A, addr8 OUT addr8, A
IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)
IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)
120
8086
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data
ADD A, data
ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
121
8086
ADC reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF
ADC A, data
ADC AL, data8 (AL)  (AL) + data8+CF

ADC AX, data16 (AX)  (AX) +data16+CF
122
8086
SUB reg2/ mem, reg1/mem
SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data
SUB A, data
SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
123
8086
SBB reg2/ mem, reg1/mem
SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF
SBB A, data
SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
124
8086
INC reg/ mem
INC reg8 (reg8)  (reg8) + 1
INC reg16 (reg16)  (reg16) + 1
INC mem (mem)  (mem) + 1
DEC reg/ mem
DEC reg8 (reg8)  (reg8) - 1
DEC reg16 (reg16)  (reg16) - 1
DEC mem (mem)  (mem) - 1
125
8086
MUL reg/ mem
MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
IMUL reg/ mem
IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
126
8086
DIV reg/ mem
DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
127
8086
IDIV reg/ mem
IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
128
8086
CMP reg2/mem, reg1/ mem
CMP reg2, reg1 Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
CMP reg2, mem Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
CMP mem, reg1 Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
129
8086
CMP reg/mem, data
CMP reg, data Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
CMP mem, data Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
130
8086
CMP A, data
CMP AL, data8 Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
CMP AX, data16 Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0
131
8086
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
132
8086
133
8086
134
8086
135
8086
136
8086
137
8086
138
8086
139
8086
4. String Manipulation Instructions
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically

updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.
140
8086

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)
REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)
141
8086

MOVS
MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) +

1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

2 142
8086

Compare two string byte or string word
CMPS
CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation

1
For word operation

2 143
8086

Scan (compare) a string byte or word with accumulator
SCAS
SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
144
8086

Load string byte in to AL or string word in to AX
LODS
LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1
LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2
145
8086

Store byte from AL or word from AX in to string
STOS
STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
146
8086
5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086
LOCK Lock bus during next instruction 147

8086
Transfer the control to a specific destination or target instruction

Do not affect flags
 8086 Unconditional transfers
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
148
8086

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Checks flags
If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP
149
8086

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0
JNE disp8 JNZ disp8 JNE disp8 JNZ disp8
Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal JBE disp8 JNA disp8
JLE disp8 JNG disp8 Jump if below or Jump if not above
Jump if less than Jump if not equal
or equal greater
150
8086
 8086 conditional branch instructions affecting individual flags
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
151
Assembler directives
8086
Microprocessor Assemble Directives
Instructions to the Assembler regarding the program being

executed.
Control the generation of machine codes and organization of the

program; but no machine codes are generated for assembler
directives.
Also called ‘pseudo instructions’
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
153
8086
DB Define Byte
DW Define a byte type (8-bit) variable
SEGMENT Reserves specific amount of memory

ENDS locations to each variable
ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and 80H –
ORG
END FFH for negative value
EVEN
EQU General form : variable DB value/ values
PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 154
8086
DB Define Word
DW Define a word type (16-bit) variable
SEGMENT Reserves two consecutive memory locations

ENDS to each variable
ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value and
ORG
END 8000H – FFFFH for negative value
EVEN
EQU General form : variable DW value/ values
PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 155
8086
DB SEGMENT : Used to indicate the beginning of

a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS
SHORT
MACRO User defined name of

the segment
ENDM 156
8086
DB Informs the assembler the name of the

program/ data segment that should be used
DW for a specific segment.
SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 157
8086
ORG (Origin) is used to assign the starting address

DB
(Effective address) for a program/ data segment
DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a
variable
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 158
8086
PROC Indicates the beginning of a procedure

DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
Program statements of the
EQU …
procedure
…
PROC RET Last statement of the

procedure
ENDP
FAR procname ENDP
NEAR
SHORT User defined name of

the procedure
MACRO
ENDM 159
8086
DB
Examples:
DW
SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …
ORG RET
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR
CONVERT ENDP
SHORT
MACRO
ENDM 160
8086
DB Reserves one memory location for 8-bit

signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS
ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
ORG displacement named AHEAD
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 161
8086
DB MACRO Indicate the beginning of a macro
DW ENDM End of a macro
SEGMENT General form:

ENDS
ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG
… the macro
END …
EVEN
EQU macroname ENDM
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 162

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8085 Architecture &

Its Assembly language programming

Interrupt Control Serial I/O Control

Timing and Control Add Buf Data/Add Buf

Control Bus (8bit)

• Serial communication Signal

• MANIPULATING THE MASKS

– The SIM instruction takes the bit pattern in the

Enable Serial Data Mask Set Enable

Not Used Force RST7.5 Flip Flop to reset

Ready IF … IE Status register

 M / is asserted high  M / is asserted low

Indicates a 1 -> 0 transition of a digital signal

Indicates a bus or a bit being in the Hi-Z state ( tri-

• Program memory - program can be located anywhere in memory.

• LDA 16 bit // load A from 0(16bit)

• IN 8bit // Accept data to A from port 0(8bit)

• SUB R // Sub A = A -B.reg

Contains a total of 74 different instructions.

M Indicates memory location

RP Indicates register pair such as BC, DE, HL, SP

 16 bit address representing address or data value.

n 8-bit address or data value stored in memory immediately after the

Cond Condition for conditional instructions. NZ (Z = 0), Z (Z =

Instruction Operation Flags

STA total total = sum

STA total total = 15

Result: 7A (All are in Hex)

CS (Code Seg Reg)

The microprocessor 8086 is operated in minimum mode

In this mode, all the control signals are given out by

In the maximum mode, the 8086 is operated by

In the maximum mode, there may be more than one

EIP IP (Intr Ptr)

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

jle 0x7 //Label_1

• The segment register can change its values to point to

- this will move the DS

0x26 0x89 0x05 0x10

“0x26” is the segment SS 2500

Multiprocess Context switching

•Segment << 4 + offset = 20 bit EA

•Segment size is a fixed 64K

The mov will store the content of AX in

0x10040 + 0x1000 = 0x11040

Why this stuff? - To get 1 MB addressing using 16-bit

ES Architecture checks if limit is

Intra and Inter process Protection

Four 16-bit segment

Code Segment (CS)

Segment Registers >> 79

Segment Code Segment Register

CS contains the base or start of the current code segment;

BIU computes the 20-bit physical address by logically

That is, all instructions of a program are relative to the

Segment Data Segment Register

Points to the current data segment; operands for most

The 16-bit contents of the Source Index (SI) or

Segment Stack Segment Register

Points to the current stack.

The 20-bit physical stack address is calculated from the

In based addressing mode, the 20-bit physical stack