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• Synchronize any asynchronous input through one path that has at least one and
preferably two flip-flops in series. The flip-flops should be running on the same
edge of your system clock as the rest of the circuit.
• Design any state machines whose operation is affected by these “synchronized”
signals to follow a gray code pattern between states controlled by these signals.
Gray Code is a counting scheme where only a single bit changes between numbers
• Ensure that setup time of the destination flip-flop is met. This will avoid the
creation of metastable conditions inside the circuit and minimize the propagation
of any should they occur.
• Compute a parity or checksum of the input data before the capture register. Latch
that into the register as well. Have the code compute parity and compare it to that
read. If there's an error, do another read.
• Use metastability hardened Flip-flops.
Noise margin
• Noise margin is a parameter closely related to the input-output voltage
characteristics. This parameter allows us to determine the allowable noise
voltage on the input of gate so that the output will not be affected.
• The specification most commonly used to specify noise margin in terms of
two parameters. LOW noise Margin NML and High noise Margin NMH
Noise Margin
• Note that if either NML or NMH for gate are reduced below
0.1*Vdd, then the gate may be susceptible to switching noise
that may be present on the inputs. Apart from considering a
single gate , one must consider the net effect of noise sources
and noise margins on cascaded gates in assessing the overall
noise immunity of a particular system.
• Rp=mRn
• BpWp=BnWn/m
• *q(k) function of routing capacitance
Clock skew
• Clock skew is a phenomenon in synchronous circuits in
which the clock signal (sent from the clock circuit or
source or clock definition point) arrives at different
components at different times.
due to
• wire-interconnect length
• temperature variations
• capacitive coupling
• material imperfections and
• differences in input capacitance on the clock inputs
• these factor became more critical for high frequency
Clock Skew--
• Negative skew
• positive skew
• Positive skew occurs when the transmitting register receives the clock
tick earlier than the receiving register.
Negative skew is occurs when the receiving register gets the clock tick
earlier than the sending reg
• Zero clock skew refers to the arrival of the clock tick simultaneously at
transmitting and receiving reg
• Useful Skew
clock skew can also benefit a circuit by decreasing the clock period
locally at which the circuit will operate correctly, it means skew add
more margin to meet setup. that is called useful skew
Clock distribution tree
• System specification
• Architecture
• Interconnect characterization ,I/O Buffer, board and connector
• Generate physical design guide lines, noise budget, Timing
Budget assessment.
• Component placement
• Constraint driven layout, final placement, critical routing
• Verification ,prototype, lab measurement.
• Meets Signal Integrality issues go ached.