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ÿ bit 7 [ [ ba Interrupt Enab e bit


1 = Enab es a interrupts 0 = Disab es a interrupts
ÿ bit 6 „ ^ Periphera Interrupt Enab e bit
1 = Enab es periphera interrupts 0 = Disab es a periphera interrupts
ÿ bit 5 p ^ TMR0 Overf  Interrupt Enab e bit
1 = Enab es the TMR0 interrupt, 0 = Disab es the TMR0 interrupt
ÿ bit 4 p^ RB0/INT Externa Interrupt Enab e bit
1 = Enab es RB0/INT externa intpt, 0 = Disab es the RB0/INT
ÿ bit 3 V ^ RB Prt Change Interrupt Enab e bit
1 = Enab es the RB prt change interrupt 0 = Disab es the RB intprt
ÿ bit 2 p ^ TMR0 Overf  Interrupt F ag bit
1 = TMR0 register has verf ed 0 = TMR0 register did nt verf 
ÿ bit 1 p^ RB0/INT Externa Interrupt F ag bit
1 = RB0/INT externa intpt ccurred 0 = The RB0/INT did nt ccur
ÿ bit 0 V ^ RB Prt Change Interrupt F ag bit
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ÿ 
PERIPHERAL INTERRUPT

ÿ „ „ V„ „ V

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ÿ „ V[ pV
ÿ p„„ ^Para e S ave Prt Read/Write Interuppt Enab e Bit
ÿ 1=Enab es the PSP read/rite interuppt 0=disenab es the PSP read/rite interuppt
ÿ p ^ A/D Cnverter interuppt Enab e bit
ÿ 1=enab es the A/D Interuppt 0=Disenab es the A/D Interuppt
ÿ V ^USART RECEIVE INTERUPPT ENABLE Bit
ÿ 1=enab es the USART receive interuppt 0=disab es the USART receive interuppt
ÿ pp ^USART Transmit Interuppt Enab e bit
ÿ 1=enab es the USART transmit interuppt 0=disab es the USART transmit interuppt
ÿ p„ ^Synchrnus Seria Prt Interrupt enab e bit
ÿ 1=Enab es the SSP Interrupt 0=Disab es the SSP Interrupt
ÿ p„ ^CCP1 Interrupt Enab e bit
ÿ 1=Enab es the CCP1 Interrupt 0=disab es the CCP1 Interrupt
ÿ pV ^TMR2 t PR2 Match interrupt Enab e Bit
ÿ 1=enab es the TMR2 t PR2 Match interrupt 0=disab es the TMR2 t PR2 Match interrupt
ÿ pV ^TMR1 OVERFLOW iNTERRUPT Enab e bit
ÿ 1=enab es the TMR1 verf  interrupt 0=disab es the TMR1 verf  interrupt
ÿ „ ^CCP2 Interrupt Enab e bit
ÿ 1=Enab es the CCP1 Interrupt 0=disab es the CCP1 Interrupt
ÿ  ^S pe A/D Cnverter cmparatr Trip Interrupt Enab e bit
ÿ 1=Enab es the S pe A/D Interrupt 0=disab es the S pe A/D interrupt
ÿ  S pe A/D TMR Overf  Interrupt Enab e Bit
ÿ 1=enab es the S pe A/D TMR Overf  Interrupt 0=disab es the S pe A/D TMR Overf  Interrupt
ÿ  EE Write Cmp ete interrupt enab e bit
ÿ 1=Enab es the EE Write cmp ete interrupt 0=disab es the EE rite cmp ete interrupt
ÿ  ^LCD Interrupt Enab e bit
ÿ 1=Enab e the LCD Interrupt 0=disab es the LCD Interrupt
ÿ  Cmparatr Interrupt Enab e bit
ÿ 1=Enab es the cmparatr interrupt 0=disab es the cmparatr interrupt
ÿ „ VV[ pV
ÿ pV ^TMR1 Overf  Interrupt F ag bit
ÿ 1=TMR1 register verf ed 0=TMR1 register did nt verf 
ÿ pV ^TMR2 t PR2 Match Interrupt F ag bit
ÿ 1=TMR2 t PR2 Match ccurred 0=N TMR2 t PR2 match ccurred
ÿ „ ^CCP1 Interrupt F ag bit Capture Mde
ÿ 1=A TMR1 Register capture ccurred 0= N TMR1 Register capture ccurred
ÿ Cmpare mde
1= A TMR1 register cmpare match ccurred 0=N TMR1 register cmpare match ccurred
ÿ PWM Mde
ÿ Unused in this mde.
ÿ „ ^ Synchrnus Seria Prt Interrupt F ag bit
ÿ 1=The transmissin/receptin is cmp ete 0=Waiting t transmit/receive.
ÿ V  ^USART Receive Interrupt F ag bit
ÿ 1=The USART receive buffer,RCRE[,is fu 0=The USART receive buffer is empty.
ÿ p  USART Transmit Interrupt F ag bit
ÿ 1=The USART transmit buffer,TXRE[,is empty 0=The USART transmit buffer is fu .
ÿ  ^ A/D Cnverter Interrupt F ag bit.
ÿ 1=An A/D cnversin cmp eted 0=The A/D cnversin is nt cmp ete
ÿ  ^S pe A/D Cnverter Cmparatr Trip Interrupt F ag bit
ÿ 1=An A/D Cnversin cmp eted 0=The A/D cnversin is nt cmp ete
ÿ  ^S pe A/D TMR Overf  Interrupt F ag bit
ÿ 1=S pe A/D TMR Overf ed 0=S pe A/D TMI did nt verf 
ÿ „„ ^Para e S ave Prt Read /Write Interrupt F ag bit
ÿ 1=A read r a rite peratin has taken p ace 0=N read r rite has ccurred.
ÿ  ^EE Write Cmp ete Interrupt F ag bit
ÿ 1=The data EEPROM rite peratin is cmp ete 0=The data EEPROM rite peratin is nt cmp ete
ÿ  ^LCD Interrupt F ag bit
ÿ 1=LCD Interrupt has ccurred 0= LCD Interrupt has nt ccurred
ÿ  ^Cmparatr Interrupt F ag bit
ÿ 1=Cmparatr input has changed 0=Cmparatr input has nt changed