Beruflich Dokumente
Kultur Dokumente
DATA-PROCESSING CIRCUITS
Multiplexers
Multiplex means many into one.
A Multiplexer is a circuit with many inputs but
only one output.
By applying control signals, we can steer any
input to the output. Thus it is called a data
selector and control inputs are termed as
select inputs.
Y=0’0’.D0+0’.0D1+0.0’D2+0.0D3
Y=D0
4-to-1 Multiplexer logic circuit:
8-to-1 Multiplexer
Logic circuit
Truth Table
A B C Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
Logic circuit 0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
Truth Table 0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15
The input bits are labeled D0 to D15. Only one
these is transmitted to the output.
map.
Realize
Y = F(A,B,C,D)=Σm(0, 2, 3, 4 ,5, 8, 9, 10, 11,
12, 13, 15) using 8-to-1 multiplexer.
Multiplexer
Nibble Multiplexer:
Demultiplexers
Demultiplex means one into many.
A demultiplexer is a logic circuit with one input
and many outputs.
2:4 DECODER
TRUTH TABLE:
INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2:4 DECODER
Boolean Expression
Y 0 = A’B’
Y1 = A’B
Y 2 = AB’
Y 3 = AB
Decoders
msb
Decoders are used in many types of applications. One
example is in computers for I/O selection as in previous
slide
Computer must communicate with a variety of external
devices called peripherals by sending and/or receiving
data through what is known as input/output (I/O) ports
Example:
Using two 2-to-4 decoders, design a logic
circuit to realize the following Boolean
function
F(A,B,C) = m(0, 1, 4, 6, 7)
Encoders
An encoder has
2N inputs
N outputs
C
The 74147
Pinout diagram Logic diagram
Exclusive-OR Gates
The exclusive-OR gate has a high output only when
an odd number of inputs is high.
Y=A B + A B
A B Y
0 0 0
0 1 1
1 0 1
Logic symbol 1 1 0
XOR gate
Truth Table
Parity Generator and Checkers
Even parity means an n-bit input has an even
numbers of 1s. For instance, 110011.
Odd parity means an n-bit input has an odd
number of 1s. For instance, 110001.
Parity Checker:
Ex-OR gate
Parity Generation
Application
To check data transmission errors
The 74180 – TTL parity generator-checker
Using 74180 to generate odd parity
CLOCKS AND TIMING
CIRCUITS
Clock waveforms
Static digital logic levels: Voltage levels that
do not change with time.
In an inverting amplifier, ii + vf -
the output voltage
changes in an opposite
direction to the input
voltage.
a) Block diagram of Magnitude comparator (b) Truth table and (c) circuit for 1-
bit comparator
MAGNITUDE COMPARATOR
X Y
X3 X2 X1 X0 Y3 Y2 Y1 Y0 X7 X6 X5 X4 Y7 Y6 Y 5 Y4 X3 X2 X1 X0 Y 3 Y 2 Y1 Y 0
+5v
15 13 12 10 1 14 11 9 15 13 12 10 1 14 11 9 15 13 12 10 1 14 11 9
4 (X > Y)in 4 4
IC 7485 3 (X = Y)in IC 7485 3 IC 7485 3
2 (X < Y)in 2 2
5 6 7 5 6 7 5 6 7
Vcc (16)
GND (8)
(X>Y)out (X=Y)out (X<Y)out (X>Y)out (X=Y)out (X<Y)out
(a) (b)
Y3=ABCD+ABCD+ABCD+ABCD
Y2=ABCD+ABCD+ABCD
Y1=ABC+ABC+ABC+ABC
Y0=ABCD
Programmable Array Logic
Commercially available PALs
10H8: 10 input and 8 output AND-OR
INVERT
PAL
PLA
HDL implementation of data processing circuits
module demux1to4(S,D,Y);
input [1:0] S;
input D;
output [3:0] Y;
reg [3:0] Y;
always @ (S or D)
case ({D,S}) //Concatenation of D and S to give 3 bits, D is MSB
3’b100 : Y= 4’b0001; //Binary representation, refer to Section 2-5. If D=1, S=00, Y=0001
3’b101 : Y= 4’b0010; // if D=1, S=01, Y=0010
3’b110 : Y= 4’b0100; // if D=1, S=10, Y=0100
3’b111 : Y= 4’b1000; // if D=1, S=11, Y=1000
default : Y= 4’b0000; //For other combinations D=0, then Y=0000
endcase
endmodule