Electronic Design Process

Introduction to VHDL

Niveaux d’abstraction pour la conception numérique

Chaque niveau d'abstraction définit un description de la circuit avec moins ou plus de

détails par rapport au niveaux inférieur ou supérieur
 Introduction to VHDL

Behavioral vs. RTL (Structural)

• Code comportemental Code structural décrit la
décrit les fonctionnalités niveau registres et porte
et le comportement de logique de circuit
la circuit
 Flot de Behavioral
conception RTL Testbench

Tech. Simulation
Synthèse
Lib.

Gate
Level

Lay-out
Simulation
Placement/routage

Simui.
FPGA ASIC Lib.
• C’est quoit VHDL?
VHSIC
Hardware
Description
Language
VHSIC – Very High Speed Integrated Circuit

Fonctions Fonctions
concurrents séquentielles

vhdl
Description Modélisation
hiérarchique de temps
 VHDL: concepts de base
• Structure générale
Votre fichier texte de
description: xxx.vhd

Mode transfert des

signaux de votre
entity

6
 VHDL: Les en-têtes de fichier
Library IEEE ;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
….
…

Le mot use : indique quelle package de la librairie nous allons utiliser

Il faut pas utiliser Numeric_std et std_logic_arith en même temps pour ne pas avoir
conflit
 VHDL: L’entité
entity sequencement is
Port (
clock : in std_logic;
reset : in std_logic;
Q : out std_logic_vector (1 down to 0)
);
End sequencement ;

Clock

Q(1:0)
sequencement
reset
VHDL: Déclaration de l'architecture

Référence à
une entité

Nom de
l’architecture
 Introduction to VHDL

The 2-to-1 Multiplexer

d0
f
d1

ENTITY mux2to1 IS
PORT( d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux2to1;
 Introduction to VHDL

d0
f
d1

• Description compartmental …
If s=0, d0 passes sur la sortie f : f=d0
If s=1, d1 passes sur la sortie f=d1
 Introduction to VHDL

d0
f
d1

ARCHITECTURE behavior OF mux2to1 IS

BEGIN
WITH s SELECT
f <= d0 WHEN '0',
d1 WHEN OTHERS;
END behavior;
 Introduction to VHDL

d0
f
d1

Description structural…
d0

f
d1

s
 Introduction to VHDL

d0

d0
f
f
d1
d1

s s

ARCHITECTURE structure OF mux2to1 IS

BEGIN
f <= (d0 AND (NOT s)) OR (d1 AND s);
END structure;
 Introduction to VHDL

Hierarchie
Un bon exemple est la construction d'un multiplexeur
(4-pour-1) à partir de 2 (Muxes 2-pour-1 ) qui seront
utilisé comme composants

d0

d1

d2

d3

s1 s0
 Introduction to VHDL

The 4-to-1 Mux

d0
d0
d1
d1 f
d2 f
dd 32

d3
s1 s0

ENTITY mux4to1 IS
PORT( d0, d1, d2, d3, s0, s1 : IN STD_LOGIC;
f : OUT STD_LOGIC);
END mux4to1;
 Introduction to VHDL

d0

d1
f
d2

d3

s1 s0

ENTITY mux4to1 IS
PORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux4to1;

ARCHITECTURE structure OF mux4to1 IS

SIGNAL I1, I2 :STD_LOGIC;
COMPONENT mux2to1
PORT(d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END COMPONENT;
BEGIN
u1:mux2to1 PORT MAP(w0, w1, sel0, I1);
u2:mux2to1 PORT MAP(w2, w3, sel0, I2);
u3:mux2to1 PORT MAP(I1, I2, sel1, f);
END structure;
 Introduction to VHDL

Processes
• Un processus est une région de code VHDL qui
exécute séquentiellement

Existe à l'intérieur de l'architecture

Plusieurs processus s’exécutent en

concurrence les uns avec les autres
 Introduction to VHDL

Processes

ENTITY orgate IS
PORT (a,b : in bit;
z : out bit);
END orgate;

ARCHITECTURE Behavior OR orgate IS

BEGIN
or_func: PROCESS (a,b)
BEGIN
IF (a='1' OR b='1') THEN
z <= '1';
ELSE
z <= '0';
END IF;
END PROCESS or_func;
END Behavior
 Introduction to VHDL

Back to the 4-to-1 Mux example…

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY ieee;
ENTITY mux2to1 IS
USE ieee.std_logic_1164.all;
PORT (d0, d1, s :IN STD_LOGIC;
USE work.mux2to1_package.all;
f :OUT STD_LOGIC);
END mux2to1;
ENTITY mux4to1 IS
PORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;
ARCHITECTURE LogicFunc OF mux2to1 IS
f :OUT STD_LOGIC);
BEGIN
END mux4to1;
f <= (d0 AND (NOT s)) OR (d1 AND s);
END LogicFunc;
ARCHITECTURE structure OF mux4to1 IS
SIGNAL I1, I2 :STD_LOGIC;
LIBRARY ieee;
BEGIN
USE ieee.std_logic_1164.all;
u1:mux2to1 PORT MAP(w0, w1, sel0, I1);
u2:mux2to1 PORT MAP(w2, w3, sel0, I2);
PACKAGE mux2to1_package IS
u3:mux2to1 PORT MAP(I1, I2, sel1, f);
COMPONENT mux2to1
END structure;
PORT (d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END COMPONENT;
END mux2to1_package;
 Introduction to VHDL

Types

ENTITY fulladd IS
PORT (a,b,Cin : IN bit;
sum, Carry : OUT bit);
END fulladd;

ARCHITECTURE struct OF fulladd IS

SIGNAL n_sum : bit;
-- other declarations
BEGIN
-- Code
END struct;
 Introduction to VHDL

Types

• When an assignment is made to a signal,

the types on either side of the signal
assignment operator must match up
ENTITY fulladd IS
PORT (a,b,Cin : IN bit;
Sum, Carry : OUT bit);
END fulladd;

ARCHITECTURE Logic OF fulladd IS

BEGIN
Sum <= a XOR b;
END Logic;
 Introduction to VHDL

Types prédéfinis

PACKAGE standard IS
TYPE boolean IS (true, false);
TYPE bit IS (‘0’, ‘1’)
TYPE character IS (-- ascii set)
TYPE integer IS range implementation_defined;
TYPE real IS range implementation_defined;
-- bit_vector, string, time
END standard;
 Introduction to VHDL

Types predefinés
 Introduction to VHDL

Standard Logic represented by IEEE 1164

• In general, std_logic should be used ALL OF

THE TIME
 Introduction to VHDL

Arrays
 Introduction to VHDL

Assignment des matrices

 Introduction to VHDL

Assignment de matrix
 Introduction to VHDL

matrices et Concatenation
 Introduction to VHDL

Arrays et Aggregates
 Introduction to VHDL

Assignment d’un matrix par nom

 Introduction to VHDL

Assignment d’un matrix par nom

 Introduction to VHDL

VHDL Operators

• Il existe 3 variétés d'opérateurs: logique, relationnel,

et arithmétique.

Les opérateurs logiques sont "et", "ou", etc

Les opérateurs relationnels sont utilisés pour

comparer les différentes valeurs

Les opérateurs arithmétiques sont utilisées pour

effectuer des fonction mathématiques
 Introduction to VHDL

VHDL Operators - Logical

• Comprend ET, OU, NAND, NOR, XOR et NOT

• Tous ont la même priorité
• Exécuter de gauche à droite
• NOT a la plus grande priorité, et exécute donc avant
d'autres opérateurs dans une expression logique.
• Les opérations logiques ne peut être appliquée que à
des matrice du même type et de même longueur
• Correspondants des éléments dans des matrice se
fait par POSITION
 Introduction to VHDL

VHDL Operateurs - Relationnel

 Introduction to VHDL

VHDL Operators - Relational

111 > 1011

 Introduction to VHDL

VHDL Operators - Arithmetic

 Introduction to VHDL

Déclarations séquentielle en VHDL

• Processes

• If-then-else

• Case
 Introduction to VHDL

Back to the Process…

 Introduction to VHDL

The IF Statement
 Introduction to VHDL

Déclaration IF-ELSIF
 Introduction to VHDL

The IF-ELSIF Statement

• The order in which statements are written in the IF-

ELSIF structure is very important
• More than one of the conditions may be true
• The first true condition causes its set of statements
to be executed
 Introduction to VHDL

The IF-ELSIF Example

 Introduction to VHDL

The CASE Statement

 Introduction to VHDL

The CASE Statement

 Introduction to VHDL

The FOR Loop

 Introduction to VHDL

Configurations

Theory behind the configuration

 Introduction to VHDL

Configurations
 Introduction to VHDL

Configurations

ENTITY mux2to1 IS
PORT( d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux2to1;

ARCHITECTURE behavior OF mux2to1 IS

BEGIN
WITH s SELECT
f <= d0 WHEN '0',
d1 WHEN OTHERS;
END behavior;

CONFIGURATION mux2to1_config OF mux2to1 IS

FOR behavior
END FOR;
END mux2to1_config;
 Introduction to VHDL

THE COMPLETE IDEA

A complete design hierarchy is defined by multiple entities, which have at

least one architecture
 Introduction to VHDL

THE COMPLETE IDEA

Each of these entities and architectures will reference standards and types
from within a stated library
 Introduction to VHDL

THE COMPLETE IDEA

Many of these entities and architectures will reference one or more

packages of common definitions
 Introduction to VHDL

THE COMPLETE IDEA

The link between each level of hierarchy, and the specification as to which
architecture will be used is provided by the configuration
 Introduction to VHDL

Packages
• A package contains a collection of definitions that
may be referenced by many designs at the same time

• Usage is similar to that of a component

• Separate design file that exists outside of the other

design units seen thus far, such as entities and
architectures
 Introduction to VHDL

User Defined Types

• Types can also be defined by the user

• A user defined type is known as an “enumerated

type”

• Types are most commonly defined inside a package,

architecture, or process

• Most synthesis tools are able to synthesize VHDL

containing enumerated types
 Introduction to VHDL

User Defined Types

• Syntax for declaring a user defined type

 Introduction to VHDL

User Defined Types

• Having defined a type, signals can be

defined of that type
• SIGNAL “state” cannot be assigned anything
which is not of type “my_state”
 Introduction to VHDL

User Defined Types

• Synthesis tools build logic from a signal which is of an

enumerated type
• Usually the minimum number of bits required to represent the
number of possible values