Chapter 6

CPU Design

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 Chapter Outline

• CPU Specification
• Very Simple CPU
• Relatively Simple CPU
• Simple CPU Shortcomings
• 8085 Microprocessor

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 Specifying a CPU

• Determine its intended applications

• Develop Instruction Set Architecture
• Design State Diagram

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CPU State Diagram

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 Instruction Cycle

• Fetch
• Decode
• Execute

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 Very Simple CPU
• 64 x 8 memory
– Address pins A[5..0]
– Data Pins D[7..0]
• 8-bit Accumulator

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 Non-ISA Registers

• 6-bit Address Register AR

• 6-bit Program Counter PC
• 8-bit Data Register DR
• 2-bit Instruction Register IR

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 Fetching Instructions from
Memory
• CPU outputs address on A[5..0]
• Delay for memory to perform its internal
operations
• Read data from memory on D[7..0]

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 Fetch States

FETCH1: AR  PC

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 Fetch States

FETCH1: AR  PC
FETCH2: DR  M

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 Fetch States

FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1

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 Fetch States

FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
FETCH3: IR  DR[7..6], AR  DR[5..0]

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Fetch State Diagram

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Decoding Instructions

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 Executing Instructions - ADD

ADD1: DR  M
ADD2: AC  AC + DR

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 Executing Instructions - AND

AND1: DR  M
AND2: AC  AC ^ DR

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 Executing Instructions - JMP

JMP1: PC  DR[5..0]

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 Executing Instructions - INC

INC1: AC  AC + 1

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 Very Simple CPU
Specification
FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
FETCH3: IR  DR[7..6], AR  DR[5..0]
ADD1: DR  M
ADD2: AC  AC + DR
AND1: DR  M
AND2: AC  AC ^ DR
JMP1: PC  DR[5..0]
INC1: AC  AC + 1

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Very Simple CPU State
Diagram

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 Establishing Data Paths
Regroup operations by destination
AR: ARPC; ARDR[5..0]
PC: PCPC + 1; PCDR[5..0]
DR: DRM
IR: IRDR[7..6]
AC: ACAC + DR; ACAC^DR; ACAC + 1

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 Establishing Data Paths

Determine functions of each component

• AR, DR, and IR only load data
• PC and AC load and increment data

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Preliminary Register Section

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 Optimize Register Section

• AR only supplies data to memory

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 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit

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 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers

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 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers
• Bus is 8-bits wide, but some registers
have fewer bits

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 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers
• Bus is 8-bits wide, but some registers
have fewer bits
• ALU needed to generate results

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Final Register Section

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Very Simple ALU

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Generic Hardwired Control
Unit

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Control Unit Design Heuristics

• Assign FETCH1 to counter value 0

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Control Unit Design Heuristics

• Assign FETCH1 to counter value 0

• Assign sequential states to sequential
values

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Control Unit Design Heuristics

• Assign FETCH1 to counter value 0

• Assign sequential states to sequential
values
• Optimize assignment of values to first
states of execute routines

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State Assignments

Instruction First State IR

ADD ADD1 00

AND AND1 01

JMP JMP1 10

INC INC1 11

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 State Assignments

Instruction First State IR Counter Value

ADD ADD1 00 1000 (8)

AND AND1 01 1010 (10)

JMP JMP1 10 1100 (12)

INC INC1 11 1110 (14)

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Very Simple CPU Control Unit

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Control Signals

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 Design Verification

0: ADD4
1: AND5
2: INC
3: JMP 0
4: 27H
5: 39H

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 Relatively Simple CPU

• 64K x 8 memory
– Address pins A[15..0]
– Data Pins D[7..0]
• 8-bit Accumulator AC
• 8-bit General Purpose Register R
• 1-bit Flag Register Z

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Instruction Set

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 Non-ISA Registers

• 16-bit Address Register AR

• 16-bit Program Counter PC
• 8-bit Data Register DR
• 8-bit Instruction Register IR
• 8-bit Temporary Register TR

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 Fetch Cycle

FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
FETCH3: IR  DR, AR  PC

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Fetch and Decode Cycles

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 NOP Execute Cycle

NOP1: (no operation)

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 LDAC Execute Cycle
LDAC1: DR  M, PC  PC + 1, AR  AR + 1

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 LDAC Execute Cycle
LDAC1: DR  M, PC  PC + 1, AR  AR + 1
LDAC2: TR  DR, DR  M, PC  PC + 1

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 LDAC Execute Cycle
LDAC1: DR  M, PC  PC + 1, AR  AR + 1
LDAC2: TR  DR, DR  M, PC  PC + 1
LDAC3: AR  DR,TR

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 LDAC Execute Cycle
LDAC1: DR  M, PC  PC + 1, AR  AR + 1
LDAC2: TR  DR, DR  M, PC  PC + 1
LDAC3: AR  DR,TR
LDAC4: DR  M

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 LDAC Execute Cycle
LDAC1: DR  M, PC  PC + 1, AR  AR + 1
LDAC2: TR  DR, DR  M, PC  PC + 1
LDAC3: AR  DR,TR
LDAC4: DR  M
LDAC5: AC  DR

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 STAC Execute Cycle

STAC1: DR  M, PC  PC + 1, AR  AR + 1
STAC2: TR  DR, DR  M, PC  PC + 1
STAC3: AR  DR,TR

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 STAC Execute Cycle

STAC1: DR  M, PC  PC + 1, AR  AR + 1
STAC2: TR  DR, DR  M, PC  PC + 1
STAC3: AR  DR,TR
STAC4: DR  AC

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 STAC Execute Cycle

STAC1: DR  M, PC  PC + 1, AR  AR + 1
STAC2: TR  DR, DR  M, PC  PC + 1
STAC3: AR  DR,TR
STAC4: DR  AC
STAC5: M  DR

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 MVAC and MOVR Execute
Cycles
MVAC1: R  AC

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 MVAC and MOVR Execute
Cycles
MVAC1: R  AC
MOVR1: AC  R

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 JUMP Execute Cycle

JUMP1: DR  M, AR  AR + 1

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 JUMP Execute Cycle

JUMP1: DR  M, AR  AR + 1
JUMP2: TR  DR, DR  M

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 JUMP Execute Cycle

JUMP1: DR  M, AR  AR + 1
JUMP2: TR  DR, DR  M
JUMP3: PC  DR,TR

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 JMPZ Execute Cycles
• JMPZY: Jump is taken

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 JMPZ Execute Cycles
• JMPZY: Jump is taken
JMPZY1: DR  M, AR  AR + 1
JMPZY2: TR  DR, DR  M
JMPZY3: PC  DR,TR

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 JMPZ Execute Cycles
• JMPZY: Jump is taken
JMPZY1: DR  M, AR  AR + 1
JMPZY2: TR  DR, DR  M
JMPZY3: PC  DR,TR
• JMPZN: Jump is not taken

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 JMPZ Execute Cycles
• JMPZY: Jump is taken
JMPZY1: DR  M, AR  AR + 1
JMPZY2: TR  DR, DR  M
JMPZY3: PC  DR,TR
• JMPZN: Jump is not taken
JMPZN1: PC  PC + 1
JMPZN2: PC  PC + 1

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 JPNZ Execute Cycles
• JPNZY: Jump is taken

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 JPNZ Execute Cycles
• JPNZY: Jump is taken
JPNZY1: DR  M, AR  AR + 1
JPNZY2: TR  DR, DR  M
JPNZY3: PC  DR,TR

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 JPNZ Execute Cycles
• JPNZY: Jump is taken
JPNZY1: DR  M, AR  AR + 1
JPNZY2: TR  DR, DR  M
JPNZY3: PC  DR,TR
• JPNZN: Jump is not taken

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 JPNZ Execute Cycles
• JPNZY: Jump is taken
JPNZY1: DR  M, AR  AR + 1
JPNZY2: TR  DR, DR  M
JPNZY3: PC  DR,TR
• JPNZN: Jump is not taken
JPNZN1: PC  PC + 1
JPNZN2: PC  PC + 1

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 Register Instructions

ADD1: AC  AC + R, IF (AC + R = 0)
THEN Z  1 ELSE Z  0

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 Register Instructions

ADD1: AC  AC + R, IF (AC + R = 0)
THEN Z  1 ELSE Z  0
SUB1: AC  AC - R, IF (AC - R = 0)
THEN Z  1 ELSE Z  0

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 Register Instructions

ADD1: AC  AC + R, IF (AC + R = 0)
THEN Z  1 ELSE Z  0
SUB1: AC  AC - R, IF (AC - R = 0)
THEN Z  1 ELSE Z  0
INAC1: AC  AC + 1, IF (AC + 1 = 0)
THEN Z  1 ELSE Z  0

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 Register Instructions

ADD1: AC  AC + R, IF (AC + R = 0)
THEN Z  1 ELSE Z  0
SUB1: AC  AC - R, IF (AC - R = 0)
THEN Z  1 ELSE Z  0
INAC1: AC  AC + 1, IF (AC + 1 = 0)
THEN Z  1 ELSE Z  0
CLAC1: AC  0, Z  1

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 Register Instructions

AND1: AC  AC ^ R, IF (AC ^ R = 0)
THEN Z  1 ELSE Z  0

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 Register Instructions

AND1: AC  AC ^ R, IF (AC ^ R = 0)
THEN Z  1 ELSE Z  0
OR1: AC  AC  R, IF (AC  R = 0) THEN
Z  1 ELSE Z  0

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 Register Instructions

AND1: AC  AC ^ R, IF (AC ^ R = 0)
THEN Z  1 ELSE Z  0
OR1: AC  AC  R, IF (AC  R = 0) THEN
Z  1 ELSE Z  0
XOR1: AC  AC  R, IF (AC  R = 0)
THEN Z  1 ELSE Z  0

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 Register Instructions

AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN

Z  1 ELSE Z  0
OR1: AC  AC  R, IF (AC  R = 0) THEN Z
 1 ELSE Z  0
XOR1: AC  AC  R, IF (AC  R = 0)
THEN Z  1 ELSE Z  0
NOT1: AC  AC, IF (AC = 0) THEN Z  1
ELSE Z  0

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Establishing Data Paths

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 Register Operations

Determine functions of each component

• AR and PC load and increment data
• DR, IR, R, and TR only load data
• AC and Z will only load data

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Preliminary Register Section

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 Optimize Register Section

• AR and IR do not send data to register

bus

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 Optimize Register Section

• AR and IR do not send data to register

bus
• Pins D[7..0] are bidirectional

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 Optimize Register Section

• AR and IR do not send data to register

bus
• Pins D[7..0] are bidirectional
• Bus is 16-bits wide, but some registers
have fewer bits

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 Optimize Register Section

• AR and IR do not send data to register

bus
• Pins D[7..0] are bidirectional
• Bus is 16-bits wide, but some registers
have fewer bits
• Register Z is not connected to anything

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Bidirectional Data Pins

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Final Register Section

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 ALU Design

LDAC5: AC0 + BUS + 0

MOVR1: AC0 + BUS + 0
ADD1: ACAC + BUS + 0
SUB1: ACAC + BUS’ + 1
INAC1: ACAC + 0 + 1
CLAC1: AC0 + 0 + 0

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ALU Design

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Generic Hardwired Control
Unit

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 Generating States

FETCH1 = T0
FETCH2 = T1
FETCH3 = T2
NOP11 = INOP ^ T3
LDAC1 = ILDAC ^ T3
LDAC2 = ILDAC ^ T4

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 Counter Control Signals

• INC = 1 when progressing through

sequential states
• CLR = 1 when returning to FETCH1

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Control Signals

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INCLUDE JAVA APPLET
ANIMATION HERE

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 Simple CPUs’ Shortcomings

• More internal registers and cache

• Multiple buses
• Instruction Pipeline
• Larger Instruction Set

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8085 Microprocessor Internal
Organization

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 Summary

• CPU Specification
• Very Simple CPU
• Relatively Simple CPU
• Simple CPU Shortcomings
• 8085 Microprocessor

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