Beruflich Dokumente
Kultur Dokumente
PROCESSING
UNIT
PRESENTED BY:
DIONALDO, SHIELA MAE G.
OBJECTIVES
• To introduce a number of CPU designs, starting with the most
simple design, then successively adding more features when
building more complex
• To learn about Minimal Design, Double Byte Instructions and
Branching, Addresses and Constants, Symmetrical Design and
its scoped topics.
CPU-1: MINIMAL DESIGN
CPU-1: MINIMAL DESIGN
CPU-1: MINIMAL DESIGN
• ALU-1 supports eight opcodes, of which only the first six are being
used (in the order of opcode 0 5): NOP, NOT, AND, OR, ADD, LOAD.
• On the CU-1 side, the program counter (PC) always addresses the
memory module and its output is fed back via an incrementer.
CPU-1: MINIMAL DESIGN
1. Load first byte of instruction (opcode) and store it in the code register.
2. Increment program counter by 1.
3. Load second byte of instruction (address) and store it in the address register.
4. Use the address value for addressing the memory and retrieving the actual
data value, which is then passed on to the ALU.
CPU-2: DOUBLE BYTE INSTRUCTIONS AND
BRANCHING
Figure 2.39
shows a much
clearer,
symmetrical
design.
CPU-4: SYMMETRICAL DESIGN
Figure 2.39
shows a much
clearer,
symmetrical
design.
CPU-4: SYMMETRICAL DESIGN
Figure 2.39
shows a much
clearer,
symmetrical
design.
CPU-4: SYMMETRICAL DESIGN