1) What are the difficulties in logic design optimization?

 Difficulties
 We may not have a logic gate for every possible function.
It may be a challenge to rewrite our combinational
logic expression so that each term represents a gate.

Not all gate networks that compute a given function are alike
-networks may differ greatly in their area and speed.
-find a network that satisfies our area and speed
requirements, which may require drastic
restructuring of our original logic expression.
2) Define the term completeness and also give an example.
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 Completeness
 A set of logical functions is complete if we can generate
every possible Boolean expression using that set of
functions
 Ex: NAND function
3)Explain about irredundancy.
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Irredundancy
Logic expression is irredundant if no literal can be
removed from the expression without changing its
truth value.
 For example, ab + ab' is redundant, because it can
be reduced to a.
4) Draw the static complementary gate that computes
a’b’ + c’d’.
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5) Find Minimum inverter delay and fall time with 

model parameters Rn =6.47KΩ and Cl = 0.89 fF.
6)Write the logic equation and draw the transistor topology
for AOI-21 gate.
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 groups of inputs are ANDed together, then all

products are ORed together and inverted for output
 Out=(ab+c)’
7)Explain about switch logic.
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 We can use switches to implement Boolean

functions.
 However, there is more than one way
to build a switch from transistors
 Parallel n-type and p-type transistors.
 it transmits logic 0 and 1 from drain to source
equally well
8) What is meant by charge sharing?
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 Domino gates are also vulnerable to errors caused by

charge sharing.
 Csd, the stray capacitance on the source and drain of the
two pulldown transistors, can store enough charge to cause
problems.
 When a=1 the pulldown connected to the storage node is
turned on, draining charge from the
storage node into the parasitic capacitance
between the two pulldowns.
9) How do you calculate Elmore delay?
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 Elmore modeled the transmission line as a sequence of n

sections of RC

 Elmore delay can be computed by taking the sum of RC

products
Delay=r4(c1+c2+c3)+r3(c1+c2) +r2c1 = r3c+r2c+rc
10) Explain about analytical model of RLC transmission line.
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 analytical/numerical model

 the 50% propagation delay of RLC transmission line

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11.a) Describe the delay and transition time analysis of

logic gates using  model. Also compare this with
current source model and fitted model.

 REFER: SOC_Unit_1_part2.ppt
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11.b (i) Analyze the power consumption of an inverter

with necessary equations

Refer : SOC_Unit_1_part2a.ppt

11.b (ii) Explain about domino logic gate structure.

Refer : SOC_Unit_1_part3.ppt
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12.a) Explain in detail about low power gates.

Refer: SOC_Unit_1_part4
 14

12.b) Discuss about the delay through an RC

transmission line with Elmore model, tapered wire,
RC trees, buffer insertion and crosstalk models.

Refer: SOC_Unit_1_part5